Executive Intelligence · Company Analysis · November 8, 2026
TSMC: The World’s Most Critical Semiconductor Foundry - TSMC manufactures the advanced semiconductors powering artificial intelligence, smartphones, cloud computing, and modern electronics. Through its pure-play foundry model, the company enables the world's leading technology businesses to turn innovative chip designs into reality. This Company Analysis examines TSMC's business model, manufacturing capabilities, financial performance, global operations, and strategic position in the semiconductor industry.
The Company That Makes the Silicon Others Design
Taiwan Semiconductor Manufacturing Company (TSMC) does not design the world’s most famous chips. It manufactures them. Nvidia’s GPUs, Apple’s A-series and M-series processors, AMD’s EPYC and Instinct silicon, Broadcom’s custom AI ASICs, Qualcomm’s and MediaTek’s mobile chips — all of them are fabricated in TSMC’s fabs, and most of them are packaged by TSMC as well. That position was not accidental. It was created in 1987 when Morris Chang founded the company on a then-radical premise: that a manufacturer could serve every chip designer in the world without competing with any of them.
The model worked. TSMC now holds roughly 72% of global foundry revenue and a share of leading-edge manufacturing that is higher still. In FY2025, the company reported NT$3,809.05 billion in revenue, a 59.9% gross margin, and NT$1,717.88 billion in net income. In Q3 2026, it reported NT$1,494.24 billion (approximately US$46.72 billion) in revenue, a 66.4% gross margin, and NT$763.06 billion in net income, with advanced nodes (7nm and below) contributing 79% of wafer revenue.
This company analysis sets out TSMC’s history, business model, technology portfolio, customer relationships, financial performance, global footprint, competitive position, and strategic priorities. It is designed to establish the company baseline — what TSMC is, how it makes money, who it serves and what it has built — that readers can use to understand the deeper strategic analysis in the companion Deep Dive and the broader AI infrastructure coverage across The CODEW.
Editorial Note: Financial figures are drawn from TSMC’s official quarterly releases and annual filings. Reporting periods and currencies are identified in every table. Company guidance is labelled as guidance and distinguished from reported results. Technologies in volume production are distinguished from those in development and from announced future roadmaps. Customer relationships described here are those publicly disclosed by TSMC or its customers; confidential arrangements and customer-specific revenue contributions are not asserted.
Company Profile
| Company | Taiwan Semiconductor Manufacturing Company |
| Common name | TSMC |
| Founded | 1987 |
| Founder | Morris Chang |
| Headquarters | Hsinchu, Taiwan |
| Industry | Semiconductor manufacturing |
| Business model | Pure-play semiconductor foundry |
| TWSE ticker | 2330 |
| NYSE ticker | TSM |
| Core business | Wafer fabrication, advanced packaging, and related semiconductor services |
| Key markets | HPC, AI, smartphones, automotive, IoT and consumer electronics |
| Major competitors | Samsung Foundry, Intel Foundry, GlobalFoundries, UMC and SMIC |
II. The Company That Built the Pure-Play Foundry Model
TSMC was founded in 1987 by Morris Chang, a semiconductor industry veteran who had spent 25 years at Texas Instruments before moving to Taiwan to lead the Industrial Technology Research Institute. Chang’s insight was that the semiconductor industry would fragment into two types of companies: those that designed chips and those that manufactured them. The designers would need a manufacturer that did not compete with them, did not sell its own branded chips, and treated every customer’s design as confidential.
That premise — the pure-play foundry model — was not obvious at the time. The dominant semiconductor companies of the era were integrated device manufacturers (IDMs) like Intel, IBM, Motorola and Texas Instruments, which designed and manufactured their own chips. The idea of a company that only manufactured, and never designed, was a structural bet on the direction of the industry.
The bet paid off. The fabless semiconductor industry — companies like Nvidia, Qualcomm, Broadcom and MediaTek, which design chips but do not manufacture them — grew up around TSMC’s model. Those companies couldn't have existed at scale without a neutral manufacturer that built their designs without competing with them. By the 2020s, when the AI boom arrived, TSMC was the only foundry that could manufacture the most advanced AI accelerators at scale, and every major AI chip designer depended on it.
TSMC was listed on the Taiwan Stock Exchange in 1994 and on the New York Stock Exchange in 1997. Its headquarters remain in Hsinchu, Taiwan, and its largest and most advanced fabs are concentrated in Taiwan, though it has expanded manufacturing to the United States, Japan, Germany, and China.
III. How TSMC Makes Money
TSMC’s revenue comes from four related activities: wafer fabrication, advanced packaging, mask making, and testing services. The core of the business is wafer fabrication — the process of turning a chip design into physical silicon on a 300mm wafer. Customers place orders for wafers, TSMC manufactures them at an agreed price, and the customer takes delivery of finished wafers that are then packaged and tested (either by TSMC or by a third-party assembly and test house).
The economics are driven by four variables: process node (leading-edge wafers command much higher prices than mature-node wafers), utilisation (a fab running at 95% utilisation generates far more revenue than one at 70%), yield (the percentage of dies on each wafer that function correctly), and capital intensity (a leading-edge fab costs $15–20 billion or more to build, and the depreciation of that investment is a permanent cost).
Advanced packaging has become a second major business. CoWoS (Chip-on-Wafer-on-Substrate), InFO (Integrated Fan-Out) and SoIC (System on Integrated Chips) are used to assemble AI accelerators by combining compute dies and high-bandwidth memory into a single package. Advanced packaging revenue is expected to exceed 10% of total revenue in 2026 and to rise above 15% in 2027.
TSMC does not sell chips. It sells manufacturing services. That distinction is fundamental to the model: it means TSMC does not compete with any of its customers, and it means its revenue is a function of how much silicon the industry needs to be manufactured rather than which specific chips win in the market. As long as someone is designing an advanced chip, TSMC has a potential customer.
Three business models, three sets of economics
Fabless (Nvidia, AMD, Broadcom, Qualcomm, MediaTek, Apple) — design chips, outsource manufacturing, capture design margin. Pure-play foundry (TSMC, UMC, GlobalFoundries) — manufacture chips for others, capture manufacturing margin and scale. IDM (Intel, Samsung) — design and manufacture their own chips, occasionally serve external foundry customers. The pure-play model is the only one that avoids a structural conflict of interest with fabless customers.
IV. Inside TSMC’s Manufacturing Technology
TSMC’s process technology portfolio spans the range from mature nodes (28nm and above) that serve automotive, industrial, and consumer applications, to leading-edge nodes (3nm, 2nm and beyond) that serve AI accelerators, data center CPUs, smartphones, and high-performance computing.
| Node | Status | Transistor architecture | Primary applications |
|---|---|---|---|
| N7 (7nm) | Volume production since 2018 | FinFET | CPUs, GPUs, mobile |
| N5 (5nm) | Volume production since 2020 | FinFET | AI accelerators, smartphones |
| N3 (3nm) | Volume production since 2022 | FinFET | AI accelerators, mobile |
| N2 (2nm) | Volume production since Q4 2025 | GAA nanosheet | AI accelerators, HPC, mobile |
| N2P | Production planned 2026–2027 | GAA nanosheet | Refinement of N2 |
| A16 | Roadmap; production targeted H2 2026 | GAA nanosheet, Super Power Rail | HPC and AI |
| A14 | Development; production targeted 2028 | GAA nanosheet (next gen) | Future HPC and AI |
Source: TSMC technology symposium disclosures and quarterly earnings commentary. “Volume production” reflects company statements. Roadmap dates are company guidance and may shift.
Why node names matter less than what they enable. The “nm” in a node name is not a direct measurement of any physical dimension. It is a marketing convention that roughly indicates the generation of the process. What actually matters is power, performance, and area (PPA) — how much computing capability can be packed into a given area at a given power budget. Moving from N5 to N3 typically improves performance by 10–15% at the same power, or reduces power by 25–30% at the same performance, depending on the design. Moving from N3 to N2 with gate-all-around transistors improves that further.
The critical role of EUV lithography. Advanced nodes from N7 onward rely on extreme ultraviolet (EUV) lithography for their most critical layers. TSMC does not manufacture EUV systems; it buys them from ASML, the sole supplier of EUV lithography at commercial scale. That dependency is a strategic fact about the entire advanced semiconductor industry: no EUV, no leading-edge chips.
2nm is the current inflection. TSMC began volume production of its N2 process in Q4 2025, with monthly output ramping from roughly 50,000–60,000 wafers in the first half of 2026 toward a target of 100,000 by the end of the year and 120,000 by early 2027. In Q3 2026, 2nm contributed 8% of wafer revenue, with 3nm at 33%, 5nm at 28%, and 7nm at 10%.
V. Advanced Packaging — The Next Layer of Manufacturing
For most of TSMC’s history, packaging was a separate industry — assembly and test houses like ASE and Amkor took finished wafers and packaged them into chips. That changed with advanced packaging, which integrates multiple dies into a single package at wafer scale. Advanced packaging is now a TSMC business in its own right, and increasingly a competitive moat.
CoWoS (Chip-on-Wafer-on-Substrate) is the flagship technology. It places a silicon interposer between the compute dies and the package substrate, allowing multiple dies and HBM stacks to communicate at high bandwidth over short distances. CoWoS is used by Nvidia, AMD, Broadcom, and hyperscaler custom-ASIC programmes, and it is one of the binding constraints on AI accelerator supply.
InFO (Integrated Fan-Out) is a wafer-level packaging technology used primarily in mobile processors, where it reduces package thickness and improves power efficiency. SoIC (System on Integrated Chips) is a 3D stacking technology that bonds multiple dies vertically, enabling tighter integration than 2.5D approaches like CoWoS. TSMC 3DFabric is the umbrella brand that encompasses all three.
Packaging capacity has become a bottleneck. TSMC’s CoWoS capacity has risen from roughly 70,000 wafers per month at the end of 2025 to more than 130,000 by the end of 2026, with a target of 200,000 in 2027 — a more than fourfold increase in three years. Even at that pace, demand outstrips supply. Advanced packaging is expected to exceed 10% of TSMC’s revenue in 2026 and 15% in 2027.
VI. The Customers Behind TSMC’s Global Business
TSMC’s customer base is the who’s who of the semiconductor industry. The company does not disclose customer-specific revenue contributions, but the relationships are publicly known through both TSMC’s and its customers’ disclosures.
| Customer | Primary products | TSMC nodes / packaging |
|---|---|---|
| Apple | A-series, M-series, S-series processors | N3, N2; InFO |
| NVIDIA | Data-center GPUs (H100, Blackwell, Rubin) | N4, N3; CoWoS |
| AMD | EPYC CPUs, Instinct accelerators | N5, N3; CoWoS |
| Broadcom | Custom AI ASICs, networking silicon | N5, N3; CoWoS |
| Qualcomm | Snapdragon mobile processors | N4, N3 |
| MediaTek | Dimensity mobile processors | N3, N2 |
| Hyperscalers | Google TPU, Amazon Trainium/Inferentia, Microsoft Maia | N5, N3; CoWoS |
Source: Public customer and TSMC disclosures. Node mappings are as publicly described by customers or TSMC and may not reflect all products or future generations. TSMC does not disclose customer-specific revenue.
Customer concentration is high but diversified across end markets. The largest customers are Nvidia, Apple, AMD, Broadcom and Qualcomm. In aggregate, these companies account for the majority of TSMC’s leading-edge revenue. But they serve different end markets — AI accelerators, smartphones, PCs, networking — which means a slowdown in one does not necessarily affect the others. That diversification is a buffer that most foundries do not have.
The distinction that matters. A company can be a TSMC customer (it buys wafers), a technology partner (it collaborates with TSMC on process development), and an ecosystem participant (its products are used in the same systems) without being the same thing. Nvidia is a customer and a close collaborator on CoWoS. Apple is a customer and a very early adopter of new nodes. Broadcom is a customer whose custom ASICs are used by Google, Meta, and OpenAI — but Google, Meta, and OpenAI are end customers of Broadcom, not direct TSMC customers. This matters because coverage that treats every company in the AI ecosystem as a TSMC customer misrepresents how the industry works.
VII. TSMC’s Financial Performance and Capital Investment
TSMC’s financial performance reflects the economics of the pure-play foundry model: high capital intensity, high margins at the leading edge, and a large base of recurring manufacturing revenue.
| Metric | FY2025 (full year) | Q3 2026 (quarter) |
|---|---|---|
| Revenue | NT$3,809.05B | NT$1,494.24B (~US$46.72B) |
| Gross margin | 59.9% | 66.4% |
| Operating margin | 50.8% | 58.7% |
| Net income | NT$1,717.88B | NT$763.06B |
| Diluted EPS | NT$66.26 | NT$29.43 |
| Capital expenditure | ~US$42B (reported basis) | 2026 guidance: US$60–64B |
| R&D expenditure | ~NT$200B+ (annual) | Reported quarterly; not separately broken out here |
Sources: TSMC FY2025 annual results and Q3 2026 quarterly results. Capex and R&D figures are approximate or drawn from guidance and should be verified against official filings before publication. Q3 2026 figures are not annualised.
Q3 2026 was a record quarter. Revenue grew 41.2% year over year and 16.2% sequentially, above guidance. Gross margin reached 66.4% — among the highest in the industry — and operating margin reached 58.7%. The company’s revenue mix shifted further toward high-performance computing, which accounted for 68% of Q3 revenue and grew 22% quarter over quarter.
Capital expenditure is the number that defines the business. TSMC plans US$60–64 billion in capex for 2026 and has said future investment will exceed previous years. That is an enormous sum for any company, and it is the price of maintaining manufacturing leadership: leading-edge fabs cost US$15–20 billion or more each, and TSMC is building them in Taiwan, Arizona, Japan and Germany simultaneously.
Revenue by technology node in Q3 2026: 2nm 8%, 3nm 33%, 5nm 28%, 7nm 10%. Advanced technologies (7nm and below) accounted for 79% of wafer revenue — a figure that reflects both the company’s leading-edge manufacturing capability and the AI-driven demand for advanced nodes.
Revenue by platform in Q3 2026: HPC 68%, smartphones 21%, IoT 4%, automotive 4%, digital consumer electronics 2%. The HPC share has grown rapidly as AI demand has accelerated, and the smartphone share — historically the largest platform — has declined as AI infrastructure spending has shifted the mix.
Dividends and buybacks. TSMC pays a quarterly dividend and has conducted share buybacks, though its primary capital allocation priority is capex for capacity expansion. The company’s cash generation remains strong enough to fund both the dividend and the capex programme from operating cash flow, which is a testament to the profitability of its leading-edge manufacturing position.
VIII. A Global Manufacturing Footprint
TSMC’s manufacturing footprint is expanding beyond Taiwan for the first time in its history, driven by customer demand for geographic diversification and by government incentives in the United States, Japan and Europe.
| Location | Status | Technology focus |
|---|---|---|
| Taiwan (Hsinchu, Taichung, Tainan) | Operational; multiple fabs; 2nm and future nodes | Leading-edge logic; CoWoS packaging |
| Arizona, USA (Fab 1) | Volume production since 2024; profitable in Q1 2026 | N4, N5 |
| Arizona, USA (Fab 2) | Construction; equipment move-in 2H 2026 | N3, volume production 2H 2027 |
| Kumamoto, Japan | Operational; profitable in Q1 2026; second fab under construction | 28nm, 22nm; specialty nodes |
| Dresden, Germany | Under construction; reported loss in Q1 2026 | Specialty nodes for automotive and industrial |
| Nanjing, China | Operational; expanded capacity under export controls | 28nm and mature nodes |
Source: TSMC disclosures and credible reporting. Status as of November 2026. Facilities under construction are not yet producing volume.
The economics of overseas fabs are different. Building and operating a fab in Arizona is more expensive than in Taiwan, and the supply chain is less mature. TSMC has said it will charge customers more for chips made outside Taiwan to reflect those costs. Whether customers will pay that premium at scale — or whether they will use the overseas fabs as a hedge while continuing to source the majority of their volume from Taiwan — is one of the open questions about the company’s expansion.
The Taiwan concentration remains extreme. The most advanced nodes — including the initial 2nm ramp — are produced in Taiwan, and the ecosystem of suppliers, talent and infrastructure that supports them is concentrated on the island. Geographic diversification is a multi-year process, not a switch that can be flipped.
IX. Competitors and the Foundry Market
The foundry market is layered: a small number of leading-edge competitors at the top, a larger group of mature-node specialists below, and a long tail of specialty fabs.
| Foundry | Market share (Q2 2026) | Model | Position |
|---|---|---|---|
| TSMC | 72.5% | Pure-play foundry | Leading edge; all major AI accelerators |
| Samsung Foundry | 5.9% | Part of IDM group | Leading edge; yield gap; Tesla 2nm win |
| SMIC | 5.4% | China foundry | Mature nodes; domestic China; export-constrained |
| UMC | 3.9% | Pure-play foundry | Mature and specialty nodes |
| GlobalFoundries | 3.2% | Pure-play foundry | Mature and specialty nodes; US footprint |
| Intel Foundry | Small but growing | IDM with external foundry | 18A and 14A; US government support |
Source: TrendForce, September 2026. Market share is Q2 2026 global foundry revenue. Intel Foundry share is not directly comparable and is described qualitatively.
Samsung and Intel are the only plausible competitors at the leading edge, but neither is close today. Samsung’s foundry business has lost share as its 3nm yield issues slowed customer adoption, though its 2nm process is improving and it has won Tesla as a customer. Intel is rebuilding its foundry business with significant government support and has secured design wins, but its external customer base remains small, and its track record on foundry execution is mixed.
The mature-node foundries — UMC, GlobalFoundries, SMIC — compete in a different market. They serve automotive, industrial, power, IoT and consumer applications that do not require leading-edge nodes. TSMC also serves these markets, but they are not where its competitive advantage or its growth lies.
X. Leadership, Innovation and Technology Strategy
TSMC’s leadership has been characterised by continuity and technical depth. C.C. Wei, who became chairman and CEO in 2024, has been with the company since 1998 and previously led its R&D and operations. Wendell Huang is the chief financial officer, and Y.J. Mii is the head of research and development. The leadership team is deeply technical and has been with the company for decades.
R&D is focused on four priorities: advancing the process roadmap from N2 to A16 and A14, developing advanced packaging technologies that enable increasingly complex AI accelerators, improving manufacturing yields and efficiency, and collaborating with customers on new designs and process nodes years before they reach production. TSMC’s R&D budget is among the largest in the semiconductor industry, and its investment in talent and equipment is a permanent cost of maintaining leadership.
The culture of execution is the most important asset. TSMC has consistently delivered on its roadmap — node after node, year after year — while competitors have slipped. That reliability is what allows customers to commit to multi-year capacity agreements and to co-develop designs against TSMC’s process roadmap. It is also the thing that would be hardest to replace if it were lost.
XI. Risks Facing the World’s Leading Foundry
TSMC’s position is strong, but it is exposed to a set of risks that are structural to the company and the industry.
Geopolitical exposure. The concentration of advanced manufacturing in Taiwan is the single largest risk. Taiwan Strait tensions, US-China technology competition, and export controls all affect TSMC’s operating environment. The company is diversifying geographically, but the leading edge will remain in Taiwan for years.
Customer concentration. A small number of customers — Nvidia, Apple, AMD, Broadcom, Qualcomm — account for the majority of TSMC’s revenue. A slowdown at one of them would affect TSMC’s business immediately.
Capital intensity and cyclicality. TSMC spends more than $60 billion a year on capex, and that investment must be recovered through volume. If AI demand slows, or if the semiconductor cycle turns down, the return on that investment will disappoint.
Overseas manufacturing costs. The company’s Arizona and Japan fabs are more expensive to build and operate than its Taiwan fabs. Whether customers will pay the premium that TSMC has said it will charge is not yet proven at scale.
Competition. Samsung and Intel are improving, and while neither can match TSMC today, the gap is narrowing. A successful Intel 14A ramp or a Samsung 2nm yield breakthrough would change the competitive landscape.
Technology and manufacturing complexity. Each new node is harder to develop and harder to yield at scale. TSMC’s track record is excellent, but the engineering challenges are growing, not shrinking.
XII. Future Outlook — The Next Era of Semiconductor Manufacturing
TSMC’s strategic priorities over the next several years are clear from its disclosed roadmap and capex guidance.
2nm expansion. The company is ramping 2nm capacity aggressively, targeting 120,000 wafers per month by early 2027 and further expansion in 2028. The 2nm node is expected to be the primary manufacturing platform for AI accelerators and high-performance computing chips over the next several years.
A16 and A14 roadmap. The A16 process, which introduces TSMC’s Super Power Rail backside power delivery technology, is targeted for volume production in the second half of 2026. A14, the next-generation node beyond A16, is targeted for 2028.
Advanced packaging expansion. CoWoS capacity is expected to reach 200,000 wafers per month in 2027, with advanced packaging revenue rising to more than 15% of total revenue. This is the key enabler for AI accelerator production, and TSMC’s investment here is as important as its investment in wafer fabrication.
Global manufacturing diversification. Arizona Fab 2 will begin volume production of N3 in 2027, and further expansions in Japan and Germany are planned. The pace of diversification depends on the economics of overseas fabs and on government incentives.
AI and HPC demand. The company expects AI-related demand to remain strong for years, and it is investing accordingly. Whether the demand materialises at the pace the industry expects is the central uncertainty in TSMC’s long-term outlook.
TSMC does not design most of the world’s best-known chips. It manufactures the silicon that allows many of the world’s leading semiconductor companies to turn their designs into products.
That position was created by the pure-play foundry model — a structural bet that chip designers would prefer to work with a manufacturer that did not compete with them. The bet worked so well that the fabless semiconductor industry grew up around TSMC, and now every major AI chip designer depends on it. The company’s financial performance reflects that: FY2025 revenue of NT$3,809.05 billion, a 59.9% gross margin, and Q3 2026 revenue of NT$1,494.24 billion with a 66.4% gross margin and 68% of revenue from high-performance computing.
The company’s competitive position is built on four layers: leading-edge process technology that competitors cannot match, advanced packaging (CoWoS, InFO, SoIC) that has become a binding constraint on AI accelerator supply, customer relationships that span decades and create switching costs, and a manufacturing scale that allows it to absorb the enormous capital requirements of leading-edge fabs. Each of these layers reinforces the others.
The risks are equally structural. Geographic concentration in Taiwan, customer concentration in a small number of very large buyers, capital intensity that requires sustained demand, and competition from Samsung and Intel that is improving even if it is not yet close. None of these risks is likely to displace TSMC in the next few years, but each is a long-term factor that management must manage carefully.
For readers who want the deeper strategic analysis — whether TSMC can sustain its dominance, how the AI boom is reshaping its competitive position, and what conditions could change the answer — The CODEW’s companion Company Deep Dive examines those questions. This company analysis has established the baseline: what TSMC is, how it operates, how it makes money, who it serves, and what it has built.
The CODEW Stat
79%. The share of TSMC’s Q3 2026 wafer revenue that came from advanced technologies (7nm and below). That figure is the clearest single measure of what TSMC is: not a general-purpose foundry competing on cost across every node, but the specialist manufacturer of the most advanced silicon in the world. It is also why the company’s fortunes are tied to the AI boom — because the customers who buy 7nm-and-below wafers are almost entirely the AI accelerator, data center, and high-end smartphone companies whose demand is growing fastest.
Sources & References
- TSMC — FY2025 annual results: revenue NT$3,809.05B, gross margin 59.9%, net income NT$1,717.88B, EPS NT$66.26 (January 2026) — investor.tsmc.com
- TSMC — Q3 2026 quarterly results: revenue NT$1,494.24B (~US$46.72B), gross margin 66.4%, operating margin 58.7%, net income NT$763.06B, EPS NT$29.43 (October 15, 2026) — investor.tsmc.com
- TSMC — Q3 2026 earnings call transcript — stockanalysis.com
- TSMC — Technology symposium disclosures on N2, N2P, A16, A14 roadmap (2025–2026)
- Futurum Group — “TSMC Q3 FY 2026 Earnings Beat and Raise on AI and HPC Demand” (October 20, 2026) — futurumgroup.com
- Pocket School — CoWoS capacity: 70K to 130K+ wafers per month; NVIDIA >50% share (August 12, 2026) — pocket.tw
- TrendForce — Global top 10 foundries Q2 2026 market share: TSMC 72.5%, Samsung 5.9%, SMIC 5.4%, UMC 3.9%, GlobalFoundries 3.2% (September 2026) — trendforce.com
- The Motley Fool — Foundry revenue ranking (September 25, 2026) — fool.com
- Taiwan News — TSMC reports profits for Arizona and Kumamoto fabs (May 16, 2026) — taiwannews.com.tw
- TweakTown — TSMC 2nm ramp: 50–60K wpm in H1 2026, 100K by year-end (August 4, 2026) — tweaktown.com
- East Asia Brief — TSMC raises 2nm wafer target to 120,000 (September 28, 2026) — eastasiabrief.com
Financial figures are company-reported and unaudited unless otherwise stated. Reporting periods and currencies are identified in every table. FY2026 capex guidance is management guidance, not deployed capital. Roadmap dates are company guidance and may shift. Technologies described as in production are distinguished from those in development and from announced future roadmaps. Customer relationships described here are publicly disclosed; TSMC does not disclose customer-specific revenue contributions. This company analysis does not provide investment advice.
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Reviewed by Erwin Castro
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Sunday, November 08, 2026
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