The HBM Revolution: Why Memory Has Become an AI Strategic Asset

Executive Intelligence Series · Special Report | September 26, 2026

High Bandwidth Memory has moved from a specialized semiconductor component to the defining constraint on AI infrastructure. UBS estimates that of the nearly $1 trillion in global AI capital expenditure projected for 2026, 90% of the incremental increase is attributable to memory costs. This Special Report examines how HBM became a strategic asset — and why the companies that control it control the pace at which AI can scale.

The HBM Revolution: Why Memory Has Become an AI Strategic Asset

Executive Overview

The HBM investment cycle represents one of the largest capital commitments in semiconductor history. SK Hynix, Samsung, and Micron Technology have committed more than $100 billion in combined HBM capital expenditure for 2026 alone. South Korea has pledged $518 billion alongside Samsung and SK hynix to build four new memory fabs and an HBM packaging hub. Micron plans up to $200 billion through 2030.

The numbers are staggering. The more important question is what that capital is buying strategically. HBM is not a commodity memory upgrade. It is a bespoke co-processor that consumes three times the wafer area of standard DRAM, requires advanced packaging that few facilities in the world can perform, and must be qualified by a customer base so concentrated that a single company — Nvidia — accounts for 58% of global demand in 2026.

HBM Capital Snapshot

Metric	2025	2026	2027 Projection
Memory Share of AI Capex	14%	37%	64%
HBM Demand Growth	—	90%	77%
HBM Supply Growth	—	—	50%
HBM4 Price Change	—	—	+65%
Nvidia Share of HBM Demand	—	58%	43%
Hyperscaler Memory Spending	$107B	~$237B	—

The CODEW Lens: HBM is not one market. It is three layers on top of each other: technology, capacity, and customer qualification. The companies that control all three control the pace of AI scaling.

The HBM Revolution: What High Bandwidth Memory Actually Is

High Bandwidth Memory is not a faster version of conventional DRAM. It is a fundamentally different architecture designed to solve a problem that conventional memory cannot address: the bandwidth gap between processors and memory.

Conventional DRAM communicates through a 64-bit interface, delivering data at rates limited by the speed of a single bus. HBM stacks multiple DRAM dies vertically and connects them through thousands of through-silicon vias, creating a wide, parallel interface that moves vastly more data per clock cycle. Where HBM3E offered a 1,024-bit interface, HBM4 doubles that to 2,048 bits, doubling the width of the data highway between memory and processor.

But raw bandwidth is only part of the story. HBM's architectural advantage lies in its proximity. By packaging the memory stack directly alongside the GPU or accelerator on a silicon interposer, HBM eliminates the latency and energy cost of transmitting data across a motherboard. The result is not just more bandwidth, but more usable bandwidth — memory that the processor can actually access at the speed it needs.

The manufacturing consequences are severe. Producing one HBM chip consumes roughly three times the wafer area of a standard DRAM chip. Every HBM stack manufactured displaces three standard memory chips that were never made. As the industry redirects wafer capacity toward HBM, conventional DRAM supply — the memory in laptops, phones, and consumer devices — has become structurally constrained. DRAM contract prices increased 58% to 63% quarter-on-quarter in Q2 2026.

HBM4 · Key Specifications

Interface width: 2,048 bits
Peak transfer rate: 13 Gbps per pin
Bandwidth per stack: 3.3 TB/s
Capacity (16-high): 48 GB
Power efficiency vs HBM3E: +40%
Thermal resistance: −10%

The CODEW Lens: HBM is not a component. It is an architectural decision that determines how fast an accelerator can compute, how much power it consumes, and how much it costs. When memory is the bottleneck, memory becomes the product.

Why AI Changed the Memory Market

For four decades, memory was a commodity. DRAM prices rose and fell with PC and smartphone cycles. Manufacturers competed on cost and scale, not differentiation. Memory was necessary, but it was not strategic. AI has changed that.

The change begins with model size. Large language models with hundreds of billions of parameters require memory capacity and bandwidth that scale with parameter count. Training a frontier model requires loading billions of parameters into memory, computing gradients, and updating weights — each step constrained by how quickly data can move between compute and memory.

Inference compounds the problem. Every token generated requires reading the model's weights from memory. Every context window held open requires storing the key-value cache — a memory structure that grows linearly with conversation length. As AI systems move from single-turn queries to multi-turn reasoning, the memory footprint per user interaction expands dramatically.

Agentic AI represents the most memory-intensive workload yet deployed. Where traditional AI inference processes a single query, an agent may execute dozens or hundreds of reasoning steps, each requiring memory to maintain state, retrieve context, and hold intermediate results. Industry analysis notes that every instance of an agent requires dedicated memory to keep its environment alive — transforming memory from an interchangeable commodity into a strategic enabler.

The economics of this shift are visible in the market data. DRAM revenue is projected to rise 177% in 2026, driven almost entirely by AI demand and the industry's pivot toward HBM. HBM demand is forecast to grow 90% in 2026, reaching approximately 33.1 billion gigabits, then grow another 77% in 2027 to 58.7 billion gigabits. JPMorgan projects a 63% compound annual growth rate in HBM bit demand from 2026 through 2028.

Memory Market Shift

Memory share of semiconductor market 2025: 30%
Memory share of semiconductor market 2026: 55%
DRAM revenue growth 2026: 177%
HBM bit demand CAGR 2026–2028: 63%
Cumulative HBM demand 2026–2028: 163B gigabits

The CODEW Lens: Memory is no longer a commodity input to computing. It is the constraint that determines how fast computing can scale. That is a structural change, not a cyclical one.

The HBM Supply Chain: Where Value and Bottlenecks Emerge

DRAM → HBM → Advanced Packaging → Interposers → Accelerators → Servers → Data Centers

The HBM supply chain is not a linear sequence. It is a series of interdependent bottlenecks, each of which can constrain the entire system. Value concentrates at the packaging stage — the step that turns DRAM dies into accelerator-ready memory stacks.

DRAM fabrication — HBM begins as standard DRAM dies manufactured on advanced process nodes (1c/1b at Samsung and SK hynix, 1γ at Micron). These dies are produced in the same fabs that manufacture conventional DRAM, meaning HBM capacity competes directly with commodity memory capacity.

TSV formation and stacking — Each DRAM die is thinned, etched with thousands of through-silicon vias, and stacked vertically. Yield at this stage is a primary determinant of HBM economics. Samsung's HBM4 yield began below 60% before improving to approximately 80%.

Advanced packaging — HBM stacks must be integrated with the GPU on a silicon interposer — a process known as 2.5D packaging. TSMC's CoWoS technology is the industry standard, and CoWoS capacity has been a bottleneck for several years. TSMC is ramping capacity from 70,000 wafers per month at the end of 2025 to 115,000–120,000 wafers per month by 2026.

Accelerator integration — Nvidia's Blackwell and Vera Rubin platforms incorporate eight to twelve HBM stacks per package. AMD's MI400, Google's TPUs, Amazon's Trainium, and Microsoft's Maia all consume HBM at varying densities. The accelerator determines the HBM specification, and the accelerator vendor determines which memory supplier qualifies.

Memory accounts for approximately 73% of CPU server costs. For AI accelerators, HBM represents the single largest component after the GPU die itself. Data-center operators absorb these costs and pass them through in cloud pricing — but the constraint is physical. Without sufficient HBM, accelerators cannot be built.

The CODEW Lens: DRAM fabrication is scale. Packaging is leverage. The companies that control packaging capacity own the integration step that turns memory into accelerators — and that is where the bottleneck actually sits.

The Three HBM Giants: Competitive Landscape

Only three companies manufacture HBM at scale. Each is pursuing a distinct capital strategy, and each faces a different set of constraints.

SK hynix — Defending the Lead

SK hynix remains the market leader by revenue share (~50% as of Q2 2026), with approximately 62% of Nvidia's HBM4 supply for the Vera Rubin platform. The company's capital program is the most aggressive in the industry: a 600 trillion won ($430 billion) cluster in Yongin, a 400 trillion won cluster in the Honam region, a 100 trillion won fab in Cheongju, and a 5.4 trillion won fab in Indiana. Its M15X fab has been fast-tracked to produce HBM4 at scale, with wafer input planned to expand from 10,000 sheets per month to 80,000.

Samsung — The Comeback

Samsung began HBM4 mass production in February 2026 using its sixth-generation 10-nanometer-class 1c DRAM and a 4-nanometer base die. Yield has climbed from below 60% to approximately 80%. The company plans to roughly double HBM4 output in 2027, increasing wafer input from 180,000 sheets per month to 250,000 — a 40% increase. Samsung's HBM revenue share rose from 21% in Q1 2026 to 33% in Q2, narrowing the gap with SK hynix from 37 percentage points to 17.

Micron — The U.S. Challenger

Micron is the only U.S.-based HBM manufacturer and is investing at a scale unprecedented in its history. Fiscal 2026 capex is expected to be above $25 billion. The company plans up to $200 billion through 2030 to expand U.S. memory capacity, including a $7 billion advanced packaging facility in Singapore. Micron signed its first-ever five-year customer supply agreement in 2026, replacing one-year contracts with binding capacity and supply commitments. All of its planned HBM output for 2026 is allocated to customers.

Company	HBM Revenue Share (Q2 2026)	Primary Advantage	Principal Constraint
SK hynix	~50%	Technology leadership; Nvidia qualification	Capacity expansion cost; capital intensity
Samsung	~33%	Vertical integration; total capacity	Demonstrating sustainable yield parity
Micron	~18%	Customer-backed capacity; U.S. supply chain	Scale relative to Samsung and SK hynix

The CODEW Lens: No single company controls all sources of advantage. SK hynix leads on technology. Samsung leads on vertical integration. Micron leads on customer-backed contracts. The competitive dynamic is one of overlapping strengths and shifting positions.

Nvidia and the HBM Connection

Nvidia is not simply a customer of the HBM industry. It is the demand signal that determines whether capital investments generate returns. In 2026, Nvidia accounts for approximately 58% of global HBM demand.

That concentration gives the company extraordinary influence over memory supplier roadmaps, qualification timelines, and pricing negotiations. When Nvidia accelerates a platform launch, memory suppliers reallocate capacity. When Nvidia simplifies quality verification to speed delivery — as it did to accelerate SK hynix's HBM4 mass production for Vera Rubin — the entire supply chain adjusts.

The concentration is expected to decline. By 2027, custom ASIC demand from hyperscalers is projected to rise to 48% of HBM consumption, surpassing Nvidia's 43% share. ASIC shipments are forecast to grow 102% year over year, compared with 15% for Nvidia. Google's TPUs, Amazon's Trainium, and Microsoft's Maia accelerators are all increasing their HBM content per chip.

AI Accelerator HBM Chain

GPU → HBM → Packaging → Networking → System → Data Center

HBM stacks per Blackwell package: 8
HBM stacks per Vera Rubin package: 8–12
SK hynix share of Vera Rubin HBM4: ~70%
ASIC HBM demand growth 2026: 82%

The CODEW Lens: HBM suppliers that secure Nvidia qualification for leading-edge nodes gain a reference customer that validates their technology for the broader market. That qualification is not a line item — it is the gate to the entire AI memory market.

The Economics of HBM: Why the Money Is So Large

HBM economics differ from traditional commodity memory in ways that make the product both more attractive and more risky.

Manufacturing complexity — HBM requires stacking multiple DRAM dies, thinning each wafer to microscopic thickness, forming thousands of TSVs, and bonding the stack with precise alignment. The 12-layer and 16-layer stacks required for HBM4 are more difficult to manufacture than the 8-layer stacks of previous generations.

Yield — Yield determines effective cost. A 60% yield means 40% of wafers are wasted, increasing the cost of each usable HBM stack by more than 60% relative to theoretical 100% yield. Samsung's improvement from below 60% to 80% is the single most important competitive development of 2026.

Capital expenditure — HBM production requires specialized equipment — wafer thinners, thermocompression bonders, metrology tools — not required for conventional DRAM. SK hynix's wafer fab equipment spending is projected at $18 billion in 2026, up 62% year over year, rising to $26 billion in 2027.

Pricing — HBM4 prices are projected to increase approximately 65% in 2027 compared with 2026 levels, with next-generation HBM4 potentially rising from approximately $2 per gigabit in H2 2026 to $4–$5 per gigabit or higher.

Gross-margin potential — HBM carries substantially higher margins than commodity DRAM, driven by differentiation and switching costs. But the margin advantage also carries risk: if capacity expands beyond demand, HBM margins could compress faster because fixed costs are higher.

Demand visibility — Micron's five-year supply agreements, SK hynix's completed 2027 HBM4 price negotiations, and Samsung's long-term contracts provide revenue visibility that commodity DRAM never offered. This visibility is what justifies the capital intensity.

Memory-cycle risks — SK hynix flirted with bankruptcy in 2001. Samsung and SK hynix both posted large losses in 2023. The current upcycle is driven by AI demand, which is real but not infinite.

The CODEW Lens: The capital intensity is not a bug. It is the barrier. Three companies can fund HBM capacity at scale. No new entrant can match their cost of capital or their accumulated process expertise.

Advanced Packaging: The Hidden Battlefield

HBM cannot be viewed independently from advanced packaging. The performance of an AI accelerator depends as much on how memory is integrated with the GPU as on the memory itself.

Current AI systems use 2.5D packaging — the GPU and HBM stacks are placed side by side on a silicon interposer, which provides electrical connections between them. TSMC's CoWoS is the industry standard, and CoWoS capacity has been a bottleneck for several years.

The packaging bottleneck is not merely a capacity problem. It is a physics problem. As HBM stacks grow taller — from 8 layers to 12 to 16 — and as the interface widens from 1,024 bits to 2,048, the thermal and electrical challenges multiply. Each additional layer increases the thermal resistance of the stack. The 2,048-bit interface requires more I/O pins, more routing layers, and more precise alignment.

The future points toward 3D integration — stacking DRAM directly on top of the compute die, eliminating the interposer entirely. Samsung has outlined a three-phase HBM roadmap culminating in zHBM, which stacks DRAM vertically on the GPU or TPU itself. This approach would improve bandwidth and energy efficiency but introduces new thermal and power-delivery challenges.

TSMC CoWoS Capacity Ramp

End of 2025: ~70,000 wafers/month
2026 target: 115,000–120,000 wafers/month
Future expansion: planned

TSMC has reportedly turned to Intel for packaging capacity — a break with industry practice that underscores the severity of the constraint.

The CODEW Lens: Packaging is not a back-end afterthought. It is the strategic bottleneck. Companies that control packaging capacity gain leverage over accelerator manufacturers, who in turn gain leverage over hyperscalers.

HBM4 and the Next Generation

HBM4 represents the most significant architectural shift in memory technology in a decade. It is not merely a faster version of HBM3E. It is a different design with different manufacturing requirements and different economics.

The interface doubles from 1,024 bits to 2,048 bits, enabling data transfer rates of 11.7 Gbps per pin at base and up to 13 Gbps at peak. Total bandwidth per single stack reaches 3.3 TB/s, approximately 2.7 times that of HBM3E. Single-stack capacity reaches 48 GB in a 16-high configuration.

Power efficiency improves by 40% compared with HBM3E. Thermal resistance is reduced by 10%, and heat dissipation capacity improves by 30%. These improvements matter because HBM power consumption is rising. A single HBM3 stack consumes approximately 10–15 watts. HBM3E consumes 12–20 watts. HBM4 is projected at 15–25 watts per stack. By HBM5, power consumption could exceed 100 watts per stack.

The technology trajectory points toward hybrid bonding — direct copper-to-copper connections between dies without solder bumps — and toward custom base dies manufactured on foundry processes, allowing memory manufacturers to integrate logic functions directly into the HBM stack.

The CODEW Lens: Each generation requires new equipment, new process flows, new packaging facilities, and new customer qualifications. The HBM4 capital race is not simply an expansion of existing capacity. It is a technology transition that requires new investment at every stage of the supply chain.

The AI Memory Bottleneck

The central question for AI infrastructure is whether memory will constrain the pace of scaling. The evidence suggests that it already does.

HBM availability — SK hynix expects HBM shortages to last at least through late 2027. Micron's entire 2026 HBM supply is already allocated, and no meaningful new capacity comes online before 2028. The supply-demand gap is projected to remain in double digits through 2028.

Power consumption — HBM4 stacks consume 15–25 watts each. An accelerator with eight HBM4 stacks consumes 120–200 watts from memory alone. Data-center power budgets are already strained by GPU power demands. The KAIST roadmap projects that HBM8-powered GPUs could consume more than 15 kilowatts per module by 2035.

Manufacturing capacity — The capacity being committed today will not produce chips until 2027 at the earliest, and in large volumes not until 2028. SK hynix's Yongin cluster begins operations in 2027. Micron's Idaho fab begins wafer output in mid-2027; the New York fab supplies memory from 2030.

Cost per accelerator — Nvidia's Blackwell platform incorporates eight HBM stacks per package. Vera Rubin is expected to incorporate eight to twelve. Each additional stack adds cost, power, and thermal load.

AI inference growth — Inference demand is recurring and distributed across customer-service systems, coding tools, search, and enterprise agents. If inference becomes the dominant workload — as most forecasts suggest — memory demand will grow more steadily and more broadly than training demand ever did.

The CODEW Lens: The timing mismatch between demand growth and capacity availability is the defining feature of the current market. Memory is not just a constraint — it is the constraint that determines how fast AI can scale.

The Capital Race: Can Investment Outrun the Cycle?

The HBM investment cycle represents one of the largest capital commitments in semiconductor history. Samsung and SK hynix have jointly committed 800 trillion won ($518 billion) to new memory fabs and HBM packaging facilities. SK hynix alone is building a $430 billion cluster in Yongin. Micron plans up to $200 billion through 2030.

The capital is flowing across six categories, each with a different strategic purpose:

Structure	Strategic Purpose	Example
Manufacturing Capacity	Largest category; multi-year projects with long construction timelines	SK hynix Yongin cluster
Advanced Packaging	Targets the bottleneck that limits HBM integration	SK hynix P&T7 ($13B)
R&D and Process Technology	New base-die architectures; hybrid bonding; thermal management	High-bandwidth flash development
Equipment	Wafer thinners, bonders, metrology tools	SK hynix $18B in 2026 (+62%)
Strategic Partnerships	Shares risk and accelerates development	SK hynix–Nvidia multi-year partnership
Customer-Backed Capacity	Ties capital to specific customer commitments	Micron five-year supply agreement

The key question is whether companies can invest aggressively enough to capture AI demand without recreating a traditional memory oversupply cycle. The industry's history suggests caution. Memory has always been a boom-and-bust business. The capital being committed today will produce capacity that must be absorbed. If AI demand growth slows before that capacity ramps, the industry faces a downturn that could be as severe as any in its history.

2027 Supply–Demand Balance

HBM demand growth 2027: 56%
HBM supply growth 2027: 50%
Gap: 6 percentage points
JPMorgan CAGR through 2028: 63%

If those forecasts hold, the capacity being built will be absorbed. If they do not, the industry faces its most expensive oversupply cycle.

The CODEW Lens: The capital race is not about investing in memory. It is about securing strategic position — technology leadership, capacity scale, and customer qualification — before the window of acute shortage closes.

Customers and Strategic Relationships

The HBM customer base is concentrated, and the relationships between suppliers and customers are becoming structural rather than transactional.

Nvidia — The largest customer, accounting for approximately 58% of HBM demand in 2026. Its qualification process is the industry's most demanding, and its platform roadmaps determine which HBM generations suppliers must produce. Nvidia has certified all three suppliers for HBM4 supply to Vera Rubin, but the allocation is skewed: SK hynix is expected to supply approximately 60%–70%, Samsung 25%–30%, and Micron the remainder.

AMD — The second-largest GPU customer. Its MI400 series accelerators incorporate HBM3E and will transition to HBM4. AMD's qualification requirements are similar to Nvidia's, but its volumes are smaller, giving it less leverage over suppliers.

Google — Designs its own TPU accelerators, which incorporate HBM at increasing densities. As a hyperscaler designing its own silicon, Google has more flexibility in memory specification but remains dependent on the same three suppliers.

Microsoft — Designs the Maia accelerator family, which incorporates HBM for AI workloads. Microsoft's Azure infrastructure is one of the largest deployments of AI accelerators globally.

Amazon — Designs Trainium and Inferentia accelerators for AWS. Amazon's custom silicon strategy reduces its dependence on Nvidia but increases its dependence on HBM suppliers.

The CODEW Lens: Qualification is the gate that determines which suppliers can serve which customers. A customer that has qualified a supplier for a specific platform cannot easily change suppliers mid-generation. That switching cost is the source of the supplier's leverage.

HBM Beyond GPUs: A Broader Computing Infrastructure Requirement

HBM demand is expanding beyond GPU accelerators, and the diversification is changing the market's structure.

Custom AI accelerators — Goldman Sachs forecasts that ASIC HBM demand will grow 82% in 2026, making up 33% of the total market. By 2027, ASIC demand is projected to rise to 48% of HBM consumption, surpassing Nvidia's 43% share. Counterpoint Research projects that HBM bit demand for ASICs will grow 35-fold by 2028.

AI inference systems — Increasing their HBM content per chip. Inference workloads require memory to store model weights and key-value caches. Systems optimized for inference — like Google's TPU and Amazon's Inferentia — incorporate HBM at densities comparable to training accelerators.

HPC and scientific computing — Have used HBM for years in supercomputers and high-performance clusters. The convergence of HPC and AI workloads is increasing HBM demand from this segment.

Networking — An emerging source of HBM demand. High-speed switches and routers require memory bandwidth to process packets at line rate. As networking speeds increase to 800G and 1.6T, HBM becomes more attractive for buffer memory and packet processing.

Emerging accelerator architectures — Including neuromorphic chips, analog AI processors, and optical computing. These may incorporate HBM or HBM-like memory in the future and represent a potential long-term source of demand.

The CODEW Lens: HBM is becoming a broader computing infrastructure requirement, not just a GPU accessory. As more types of processors incorporate HBM, the memory layer becomes more central to the computing stack — and the companies that control HBM supply become more strategically important.

Who Controls the AI Memory Layer?

Strategic control over HBM does not rest with a single company. It is distributed across multiple sources of advantage, each of which can determine outcomes in different market conditions.

Technology — SK hynix leads in HBM3E and HBM4 technology, with the highest speeds and the earliest qualification with Nvidia.

Manufacturing scale — Samsung has the largest total memory production capacity and the most vertically integrated structure.

Yield — A company with 80% yield can produce more usable HBM from the same wafer input than a company with 60% yield. Samsung's yield improvement is the single most important development in the competitive landscape in 2026.

Packaging — SK hynix's P&T7 and Indiana facilities give it the most packaging capacity outside of TSMC.

Capacity — SK hynix's M15X expansion — from 10,000 to 80,000 wafers per month — is the most aggressive single-facility expansion in the industry.

Customer qualification — Nvidia's qualification is the most valuable credential in the HBM industry.

Capital — SK hynix's $430 billion Yongin cluster, Samsung's $518 billion joint commitment with the Korean government, and Micron's $200 billion U.S. investment plan all represent capital at a scale that smaller competitors cannot match.

Supply-chain relationships — SK hynix's multi-year technology partnership with Nvidia, Samsung's vertically integrated structure, and Micron's five-year customer agreements all create structural advantages.

The CODEW Lens: No single company controls all sources of advantage. The competitive dynamic is one of overlapping strengths and shifting positions. Strategic control is distributed — and that distribution is what makes the market interesting.

Strategic Risks: What Could Break the HBM Cycle

The HBM investment cycle carries risks that could reshape the competitive landscape.

AI demand slowdown — Hyperscaler capex-to-EBITDA ratios have already exceeded 70% in 2026, with some companies expected to spend more than their EBITDA in 2027. If AI infrastructure spending plateaus, the demand signal that justifies current HBM capacity commitments weakens.

Memory oversupply — Morningstar analyst Jing Jie Yu warns that "accelerating capex over the next decade further increases the risk of an oversupply longer term." Former SEC Chair Gary Gensler has said memory suppliers will eventually "lose what's called pricing power" as shortages ease.

Rapid technology transitions — The transition from HBM3E to HBM4 required new equipment and new process flows. The transition from 2.5D to 3D packaging will require another set of investments.

Customer concentration — Nvidia's 58% share of HBM demand means that a single customer's capex revision can ripple through the entire supply chain.

Capital intensity — HBM production requires more capital per unit of output than commodity DRAM. The payback period is longer, and the equipment is specialized.

Competitive catch-up — Samsung's yield improvements and revenue share gains show that the gap between SK hynix and its competitors is narrowing.

Packaging constraints — TSMC's CoWoS capacity, HBM packaging capacity, and interposer supply all must expand in coordination. A bottleneck in any one step constrains the entire system.

Alternative memory technologies — High-bandwidth flash, magnetic RAM, and resistive RAM could eventually reduce dependence on HBM.

The CODEW Lens: The timing mismatch between demand growth and capacity availability is the single largest risk in the HBM capital cycle. Much of the capacity being committed today will not produce chips until the window of acute shortage has potentially closed.

The Bigger AI Infrastructure Picture

Power → Data Center → Compute → HBM → Networking → Storage → Cloud → AI Models → Applications

HBM is not an isolated component. It is a layer in a stack that spans power, data centers, compute, networking, storage, cloud, AI models, and applications.

Each layer depends on the ones below it. Power determines how many accelerators a data center can support. Data-center capacity determines how many accelerators can be deployed. Compute performance depends on HBM bandwidth. Networking connects accelerators into clusters. Storage feeds training data and archives inference outputs. Cloud makes the compute available to users. AI models consume the compute. Applications deliver value to end users.

HBM sits at the center of this stack, between compute and networking. It is the memory that makes compute useful and the bandwidth that makes networking necessary. Without sufficient HBM, accelerators cannot be built. Without accelerators, AI models cannot run. Without running models, applications cannot deliver value.

The strategic importance of HBM derives from this position. It is not a commodity input that can be substituted or deferred. It is a gating factor that determines the pace at which AI infrastructure can expand. When memory is the bottleneck, memory suppliers hold leverage over accelerator manufacturers, hyperscalers, and ultimately the entire AI economy.

The CODEW Lens: The companies that control HBM supply — SK hynix, Samsung, and Micron — control a critical layer of the AI infrastructure stack. Their capital strategies, technology roadmaps, and customer relationships are shaping the pace of AI's expansion.

The CODEW Takeaway

If compute is the engine of AI, HBM is the fuel line.

The evidence from 2026 supports a structural argument: memory has become a strategic layer of computing, not merely another component. Three observations support this conclusion.

First, AI workloads are memory-bound by design. Model performance scales with memory bandwidth and capacity. Training a frontier model requires loading billions of parameters. Inference requires reading those parameters and storing key-value caches. Agentic AI multiplies the memory footprint per user interaction. Compute without memory is an engine without fuel.

Second, the supply chain cannot expand fast enough to meet demand. HBM capacity takes 18 to 24 months to build. The capacity being committed today will not produce chips until 2027 or 2028. SK hynix expects shortages through late 2027. Micron's 2026 supply is fully allocated. The gap between demand growth (56% in 2027) and supply growth (50%) is narrowing but not closing.

Third, the capital required to expand capacity is at a scale that only three companies can sustain. SK hynix's $430 billion Yongin cluster, Samsung's $518 billion joint commitment with the Korean government, and Micron's $200 billion U.S. investment plan represent capital at a scale that no new entrant can match. The barriers to entry in HBM are not just technical — they are financial.

The CODEW verdict: HBM suppliers have become gatekeepers to the AI economy. Their capacity decisions determine how many accelerators can be built. Their qualification decisions determine which platforms can launch. Their pricing decisions determine the cost of AI infrastructure. This is a level of strategic influence that memory manufacturers have never held before. The risk is that the current shortage eventually becomes overcapacity — but even in a downturn, memory will remain more strategically important than it was before AI.

The CODEW Lens: The question is not whether memory matters. It is how much leverage suppliers can sustain as capacity expands. For now, the answer is clear: HBM is the constraint that defines how fast AI can scale.

The HBM Glossary

HBM (High Bandwidth Memory) — A memory architecture that stacks multiple DRAM dies vertically and connects them through through-silicon vias, delivering bandwidth far exceeding conventional DRAM.

HBM4 — The fourth generation of HBM, doubling the interface to 2,048 bits and introducing semi-custom logic dies manufactured on foundry processes.

TSV (Through-Silicon Via) — A vertical electrical connection passing through a silicon die. Thousands of TSVs connect each HBM stack.

Advanced Packaging — The 2.5D and 3D integration of HBM with GPUs on a silicon interposer. The narrowest bottleneck in the HBM supply chain.

CoWoS — TSMC's Chip-on-Wafer-on-Substrate packaging technology, the industry standard for 2.5D integration of HBM with accelerators.

Customer-Backed Capacity — A financing structure in which a memory manufacturer commits capacity in exchange for multi-year customer supply commitments.

JEDEC Standard — The industry specification body for memory. HBM4 JEDEC standard bandwidth is 8 Gbps per pin; Nvidia's Vera Rubin requires higher speeds.

MR-MUF — Advanced packaging technology used in HBM stacking; more complex for 16-layer configurations.

Hybrid Bonding — Direct copper-to-copper connections between dies without solder bumps; enables higher stacking densities and better thermal performance.

ASIC HBM Demand — HBM consumed by hyperscaler-designed custom accelerators (Google TPU, Amazon Trainium, Microsoft Maia) rather than Nvidia GPUs.

Memory Cycle — The historical boom-and-bust pattern of the DRAM industry, driven by capacity additions outrunning demand growth.

zHBM — A future architecture that stacks DRAM vertically on the GPU or TPU itself, eliminating the interposer entirely.

FAQ

Q: Why has memory become a strategic constraint in AI infrastructure?

AI workloads are memory-bound by design. Model performance scales with memory bandwidth and capacity, not just compute. Training requires loading billions of parameters. Inference requires reading those parameters and storing key-value caches. Agentic AI multiplies the memory footprint per user interaction. Memory represents 37% of AI capex in 2026, up from 14% in 2025, and is projected to reach 64% by 2027.

Q: How much is being invested in HBM capacity?

Samsung and SK hynix have committed more than $100 billion in combined 2026 HBM capex. South Korea has pledged $518 billion alongside its memory champions. SK hynix alone is building a $430 billion cluster in Yongin. Micron plans up to $200 billion through 2030.

Q: Who are the major HBM suppliers?

Only three companies manufacture HBM at scale: SK hynix (~50% revenue share), Samsung (~33%), and Micron (~18%). SK hynix leads on technology and Nvidia qualification. Samsung leads on vertical integration and total capacity. Micron leads on customer-backed contracts and U.S. supply-chain positioning.

Q: Why does Nvidia's demand matter so much?

Nvidia accounts for approximately 58% of global HBM demand in 2026. That concentration gives it extraordinary influence over memory supplier roadmaps, qualification timelines, and pricing negotiations. By 2027, custom ASIC demand from hyperscalers is projected to rise to 48% of HBM consumption, surpassing Nvidia's 43% share — diversifying the customer base but not eliminating the premium customer's influence.

Q: Is the HBM capital race structural or temporary?

Both. It is a temporary response to an acute shortage — capacity being built to meet demand that currently exceeds supply. But it is also the beginning of a structural reallocation of capital toward memory as a critical layer of computing. The capital is buying strategic position, not just capacity.

The CODEW Stat

90% of incremental AI capex · $518B South Korea commitment · 58% Nvidia HBM demand Of the approximately $998 billion in total AI capex projected for 2026, 90% of the incremental increase is attributable to memory costs. South Korea, Samsung, and SK hynix have jointly committed $518 billion to build four new memory fabs and an HBM packaging hub. And Nvidia alone accounts for 58% of global HBM demand. The HBM capital race is not simply a semiconductor investment cycle. It is a structural reallocation of capital toward memory as a critical layer of computing.

The CODEW