Semiconductor Watch: Qualcomm Sticks With TSMC for Flagship Chips as Samsung Advances Next-Gen DRAM

Watch Tech Series · Semiconductor Watch | September 25, 2026

TSMC pricing power, the 2nm foundry fight, EDA certification, the memory market beyond HBM, and Taiwan's next packaging buildout — this week's semiconductor stack, top to bottom.

AI demand isn't just filling order books — it's giving suppliers pricing power at every layer of the chip stack. This edition moves down that stack in order: foundry pricing, process-node competition, the EDA tools that make advanced nodes usable, the memory market being reshaped around HBM, and the packaging infrastructure that increasingly decides which accelerators actually ship.

1. TSMC Reportedly Prepares Another Wafer Price Increase

Source: Digitalize

Citing supply-chain sources, Digitalize reports that TSMC is planning wafer price increases of 3% to 6% starting January 2027, with order visibility now reportedly extending toward 2030. That figure comes from sourced reporting, not confirmed TSMC guidance, and should be read that way until the company says otherwise.

If accurate, it's the clearest sign yet that AI demand has converted into durable pricing power rather than a temporary capacity crunch. A multi-year order backlog gives TSMC room to raise prices without losing customers who have nowhere else to go for leading-edge capacity — a dynamic that flows straight through to AI accelerator bill-of-materials costs, fabless margins, and hyperscaler infrastructure budgets. It also strengthens TSMC's negotiating position against Samsung Foundry and Intel Foundry, both of which need marquee customers more than TSMC needs any single one.

2. Qualcomm Sticks With TSMC for 2nm Flagship Chips

Source: Digitalize

Qualcomm is reportedly planning to build both of its next-generation 2nm Snapdragon flagship platforms on TSMC, even as Samsung Foundry continues courting advanced-node customers. Without reliable performance data on the table, the more useful read isn't a benchmark comparison — it's a customer-concentration story.

For TSMC, retaining Qualcomm at 2nm reinforces the order-book depth behind story #1's pricing power. For Samsung Foundry, it's another sign that a competitive technology roadmap on paper hasn't yet translated into major flagship wins — yield and packaging support tend to matter as much as node specs when a customer the size of Qualcomm decides where to commit volume. Samsung's actual test isn't whether it can design a 2nm process; it's whether it can convert that roadmap into signed customers.

3. Cadence and Synopsys Certify TSMC A14 Design Flows

Source: Digitalize

Cadence and Synopsys have certified key design flows for TSMC's upcoming A14 process, ahead of risk production in 2027 and volume production in 2028. It's easy to treat this as a footnote next to fab-level news, but the EDA layer is part of the competitive moat, not a supporting act.

A new process node is unusable to chip designers until the software that lays out, verifies, and simulates circuits on that node is certified and stable. Early Cadence/Synopsys certification lets design teams start real A14 work years before volume production begins, which is exactly what lets TSMC's next generation of customers tape out chips on day one of the node's availability rather than waiting a design cycle behind. That head start is as much a reason customers stay with TSMC as raw transistor density is.

4. Memory Competition Shifts Beyond HBM

Source: Digitalize

Digitalize reports that China's CXMT is gaining ground in conventional DRAM even as Samsung and SK Hynix reallocate their own capacity toward HBM to feed AI accelerator demand. The two trends are connected: every wafer Samsung and SK Hynix shift to HBM production is a wafer not making standard DRAM, and CXMT is filling part of that gap.

That tension — AI accelerators pulling HBM supply away from the broader memory market while Chinese producers expand into the resulting shortfall — is the kind of structural shift worth flagging alongside our AI Infrastructure Intelligence coverage. If it continues, expect conventional DRAM pricing to firm up even for buyers with no direct exposure to AI hardware, simply because capacity that used to serve them is being redirected.

5. Samsung Explores Hybrid Bonding for Next-Generation DRAM

Source: Digitalize

Samsung is reportedly revising its roadmap for its first sub-10nm DRAM generation around wafer-to-wafer hybrid bonding — a technique that fuses two wafers directly together at the atomic level, rather than stacking and wiring chips as separate finished pieces. In plain terms: instead of just making transistors smaller to fit more memory on a chip, Samsung is looking at building memory in vertical layers bonded together more tightly than before.

That's consistent with where the whole industry is heading. Shrinking transistors is running into physical limits that get more expensive to push past every generation, while bonding and stacking techniques offer another way to add capacity and bandwidth. The next memory race is increasingly a packaging and manufacturing race as much as a lithography one.

6. Taiwan Builds Out Advanced Packaging Infrastructure

Source: Reuters

Taiwan has broken ground on a new advanced-packaging industrial park in Kaohsiung, anchored by a TSMC technology-validation lab and talent-training center, with operations expected in Q4 2029. Reuters reports the park is designed to support equipment and materials suppliers and strengthen Taiwan's advanced-packaging ecosystem broadly, not just TSMC's own operations.

Advanced packaging has become strategic infrastructure in its own right. The AI accelerators shipping from Nvidia, AMD, and Broadcom depend on TSMC's packaging technologies — CoWoS and its successors — as much as they depend on the underlying process node, since stacking compute and memory dies together is what lets those chips hit their performance targets. A dedicated industrial park with its own supplier base and training pipeline is Taiwan betting that packaging capacity, not just fab capacity, is the next constraint the industry needs to build around.

Market Context: AMD Crosses the $1 Trillion Mark

AMD surpassed a $1 trillion market capitalization on September 21 as investors responded to its expanding AI business. Reuters notes the company has moved beyond selling individual chips toward complete systems combining processors, networking, and related hardware — a framing worth sitting alongside everything above it in this edition. The competitive line in semiconductors is drawn less around who designs the fastest single processor and more around who controls the surrounding system: the foundry relationship, the packaging, the networking, and the memory it all ships with.

The CODEW Semiconductor Intelligence Takeaway

The semiconductor race is moving deeper into the infrastructure stack. None of today's developments are about who designs the fastest processor. They're about who controls the layers underneath it:

• advanced-node capacity
• wafer pricing
• EDA software
• HBM and DRAM allocation
• advanced packaging
• foundry relationships
• manufacturing ecosystems

Every name in this edition — TSMC, Qualcomm, Samsung, Cadence, Synopsys, CXMT, SK Hynix, AMD — is competing somewhere on that list, not just on chip design. That's the throughline that separates a Semiconductor Watch edition from a list of unrelated chip headlines.

Sources

→ Digitalize — TSMC wafer pricing, Qualcomm/TSMC 2nm, memory and Samsung developments
→ Digitalize — TSMC A14, advanced manufacturing and EDA ecosystem developments
→ Reuters — Taiwan advanced-packaging industrial park and TSMC ecosystem
→ Reuters — AMD's $1 trillion milestone and move toward complete AI systems
→ Investing.com / Reuters — ASML's longer-term High-NA roadmap and implications for Intel, TSMC and Samsung

THE CODEW · SEMICONDUCTOR WATCH

Editorial Note

Semiconductor Watch tracks the developments reshaping AI infrastructure, advanced manufacturing, memory, foundries, packaging, chip design, and semiconductor supply chains.

Educational content only. Not investment advice. Analysis is based on company announcements, official disclosures, and reporting from Digitalize, Reuters, and Investing.com cited above. Figures attributed to sourced reporting rather than confirmed company guidance are noted as such in the text. Coverage reflects the sources and reporting period referenced.