Semiconductor Watch · October 6, 2026
Power, memory, packaging, foundry capacity, and interconnects are becoming one connected bottleneck: the AI chip story is turning into a systems-capacity story.
Core Research Question
Is the AI semiconductor constraint moving from compute availability to a connected systems problem of power, memory, packaging, foundry capacity, and interconnects?
1. From Chip Shortage to Systems Capacity
For three years, the AI semiconductor story was about whether enough accelerators could be made. The evidence this week points somewhere else. The constraint is moving to everything that has to arrive at the same time as the chip: electricity, high-bandwidth memory, advanced packaging, foundry capacity, power conversion and optical interconnects.
Each story below sits at a different point on that chain. Read together, they describe an industry whose bottlenecks are interconnected: a delay in one layer, such as power, propagates into demand for the others.
The CODEW angle: The question for investors and buyers is no longer "who makes the best GPU?" It is "which layer is scarce this quarter, and who owns it?"
2. Nvidia and Broadcom Face a Different Kind of AI Bottleneck
Reuters reported on October 5 that Morgan Stanley sees Nvidia and Broadcom as comparatively shielded from the U.S. data-center power crunch, while the supply chain behind them is more exposed. The risk is that power shortages delay data-center deployments, which would defer demand for memory, optical and power-related components even if accelerator orders hold. The note adds to a broader argument from the bank: on October 2 it reinstated Nvidia as its top semiconductor pick while saying the AI buildout is increasingly constrained by power, construction and financing rather than GPU supply.
The scale of the gap is large. Morgan Stanley's August research put U.S. data-center power demand at about 68 GW between 2026 and 2028, with roughly 30 GW covered by projects under construction and available grid capacity. Reuters' latest account cites a net shortfall of about 32 GW through 2028; we could not open the full Reuters article, so that figure is attributed to its reporting.
The CODEW angle: Shielded does not mean immune. A chip order that cannot be installed becomes a revenue timing risk further down the supply chain, first for memory and optics.
3. Intel vs. TSMC: Terafab Becomes a Foundry Credibility Test
Elon Musk confirmed on October 3 that early talks with TSMC could bring it into Terafab, writing that they are "just discussions, but something may come of it." The Culpium newsletter reported a day earlier that TSMC is exploring ways to help Terafab run its planned Texas factories, with the likeliest structure being a TSMC-owned and operated fab with Terafab as anchor customer, similar to TSMC's JASM venture in Japan and ESMC in Germany.
Intel joined Terafab in April, and Musk later said the full-scale plant would use Intel's 14A process, but SpaceX's registration reportedly described only a general framework, with financial terms and Intel's continuing participation subject to later agreements. Intel shares fell roughly 2% to 4% on October 5 as investors weighed what shared sourcing means. Intel's external foundry revenue was just $293 million in the second quarter, so few outside wins are as visible as Terafab. Total project spending could reach as much as $119 billion across phases, according to county filings.
TSMC has not commented, and no agreement has been announced. Intel's 14A design kit, due this month, is the next concrete checkpoint.
The CODEW angle: This is dual sourcing until proven otherwise. But Terafab is Intel's showcase customer, and a credible second foundry means Intel must win on execution, not on being first.
4. Foundry Capacity Moves Toward Advanced Packaging and Photonics
Advanced packaging is where foundry capacity is being allocated. TrendForce said on September 18 that the silicon interposer behind CoWoS-S is nearing physical limits as chips grow and carry more HBM, pushing the industry to CoWoS-L, which embeds silicon bridges. Nvidia and AMD accelerators already use it, Meta's MTIA 400 does too, and AWS and Microsoft are expected to follow in 2027. Larger interposers raise cost, and persistent TSMC packaging constraints are increasing interest in Intel's EMIB as an alternative.
TSMC says its 5.5-reticle CoWoS is in volume production with yields above 98%, targets a 14-reticle package in 2028, and has nearly doubled CoWoS capacity each year for three years. It also flagged memory and ABF substrate as bottlenecks. In parallel, TSMC is integrating silicon photonics into its HPC platform, and mature-node foundries are positioning for it: UMC licensed imec's silicon-photonics process, which fits 28nm and 22nm nodes. TrendForce's October 5 foundry bulletin was not accessible to us, so this section draws on its earlier reporting.
The CODEW angle: Leading-edge wafers are no longer the only scarce foundry resource. Packaging and photonics capacity now decide how many accelerators actually ship.
5. 800V Power Architecture Creates a New Semiconductor Opportunity
Navitas and Microchip announced on October 5 an 800V DC-to-6V DC reference design for AI data-center racks, aligned with the Open Compute Project's 800V DC standard. It pairs Navitas GaNFast power devices with Microchip digital controllers and a security chip, and the companies target up to 96% peak efficiency at full load and a power density of 2,100 W per cubic inch. The design collapses two conversion stages into one and will be shown at the OCP Global Summit in San Jose on October 12 to 15.
The context is Nvidia's push toward 800V DC distribution, which Navitas says avoids the 200 kilograms or more of copper a 54V system would need for a 1 MW rack. Texas Instruments and STMicroelectronics announced their own 800V-related products at GTC, and ST noted that 50V, 12V and 6V buses will coexist depending on rack design.
The CODEW angle: AI infrastructure is creating a second semiconductor market in GaN, SiC, controllers and power conversion. It also gives those suppliers a direct stake in the power constraint.
6. HBM and Memory Remain Central to the AI Cycle
The memory market is tight and structurally slow to loosen. Samsung's CFO said earlier this year that its HBM4 volume for 2026 was completely sold out, and Micron has said its 2026 HBM production was committed. One September analysis notes that major SK hynix capacity projects target cleanroom and volume output only from 2028 to 2029.
Pricing reflects that scarcity. TrendForce News reported in August that HBM contract prices could rise by more than 50% in 2027 after a reported Nvidia server price increase. That is also why the Morgan Stanley warning matters: memory makers are among the suppliers most exposed if power-driven delays slow AI-server installations.
The CODEW angle: HBM is both the scarcest component and one of the most exposed to deployment timing. Tight supply and delayed demand can coexist.
7. Silicon Photonics and Optical Interconnects Move Toward Standards
Optical connectivity is maturing from custom engineering toward standardization. JEDEC's JC-14.3 committee has advanced a silicon-photonics qualification and reliability standard, JESD264, led by a Cisco-chaired task group, built around a "qualify once" platform approach that replaces case-by-case customer negotiations. That addresses one of the main objections to co-packaged optics: reliability.
Lumentum, meanwhile, will present on external laser sources for deployable CPO-based AI networks, 12.8T VCSELs and optical circuit switching at the OCP Global Summit on October 14 and 15. A TSMC executive has said silicon photonics could account for more than 50% of the optical transceiver market by 2027.
The CODEW angle: Standards turn photonics from a bespoke bet into a supply-chain category. That is what lets volume suppliers, foundries and packagers plan capacity around it.
8. The Semiconductor Bottleneck Map
Six constraints now sit between an accelerator order and a working AI cluster. This table maps each to this week's evidence.
| Power | Grid access and on-site generation decide when data centers energize; Morgan Stanley flags a multi-gigawatt shortfall. |
| Memory | HBM sold out for 2026 and exposed to deployment timing; new capacity mostly 2028 or later. |
| Packaging | CoWoS-L, larger interposers and EMIB alternatives; TSMC still the capacity gatekeeper. |
| Foundry | Terafab shows leading-edge capacity may be shared across Intel and TSMC rather than awarded to one. |
| Power conversion | 800V DC and GaN/SiC create new silicon content per rack. |
| Interconnect | Silicon photonics and CPO move toward standardized qualification. |
The CODEW angle: The bottleneck is not disappearing; it is moving downstream from the chip toward power, memory, packaging, and connectivity. The next winners are likely the suppliers that own the scarcest of those layers.
The CODEW Angle
AI infrastructure is turning semiconductor constraints into a systems problem: power, memory, packaging, foundry capacity and interconnects now limit one another.
The industry is moving from a chip-shortage story to a systems-capacity story. A GPU is only as valuable as the power, HBM, package, and network available to make it useful, and every layer has its own lead time.
For the AI infrastructure race, that means competitive advantage is shifting toward companies that control a scarce layer or can coordinate several of them. It also means deployment timing, not only chip demand, will drive supplier results over the next several quarters.
Sources
→ Reuters: Nvidia, Broadcom shielded as AI power crunch hits chip supply chain, says Morgan Stanley
→ ROIC.ai: Morgan Stanley reinstates Nvidia as top semiconductor pick
→ 24/7 Wall St.: AI data center power shortfall (Morgan Stanley research)
→ Yahoo Finance / Investing.com: Intel stock slides as TSMC explores Terafab tie-up
→ 24/7 Wall St.: Intel drops as Musk signals TSMC could join Terafab
→ TIKR: Intel drops as Musk signals TSMC could join Terafab
→ TrendForce: CoWoS-L to remain mainstream advanced packaging through 2028
→ TrendForce News: TSMC 5.5-reticle CoWoS tops 99% yield; flags memory, ABF as bottlenecks
→ TrendForce News: TSMC on SoIC, CoWoS and silicon photonics
→ Semiconductor Today: Navitas and Microchip collaborate on 800V reference design
→ Embedded.com: Nvidia GTC, more support for 800-VDC data centers
→ IntuitionLabs: HBM, DRAM and AI demand, memory supply and price trends
→ IEEE: Silicon Photonics Qualification and Reliability Requirements (JEDEC)
→ Lumentum: Speaker lineup at 2026 OCP Global Summit
The CODEW Stat
6 developments · ~32 GW reported U.S. net power gap · $119B potential Terafab scale · 6 layers of the AI chip supply chain
Today's stories span six distinct constraints. None of them is the accelerator itself.
Editorial Note
Semiconductor Watch is the fast-moving intelligence layer tracking what is changing now in AI chips, memory, foundries, advanced packaging, equipment and chip supply chains, distinct from Company Analysis, Company Deep Dive and Evergreen Intelligence on topics such as HBM and AI accelerator architectures.
This edition examines where the semiconductor bottleneck is moving, drawing on Reuters, TrendForce, Semiconductor Today, company newsrooms and financial-press reporting as of October 6, 2026.
Educational content only. Not investment advice. Terafab and TSMC discussions are unconfirmed and early-stage; power-shortfall figures are Morgan Stanley estimates as reported by Reuters and other outlets; vendor performance claims are reported as disclosed and have not been independently verified by The CODEW.
Reviewed by Erwin Castro
on
Tuesday, October 06, 2026
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