Semiconductor Watch: The AI Chip Race Is Now Systems Race; HBM & Advanced Packaging Becomes Next Battlefield

Semiconductor Watch | September 18, 2026

The AI Chip Race Is Entering Its Next Phase: Beyond GPUs

The Big Semiconductor Story

The Systems Race Begins

For the past three years, the AI chip conversation has been dominated by a single question: who has the fastest GPU? Nvidia's data center revenue has grown from $15 billion to over $100 billion annually, and its H100 and Blackwell processors have become the defining hardware of the generative AI era. But as AI workloads scale from experimentation to production, the semiconductor industry is pivoting toward a more complex question: who can build the entire semiconductor system required to run AI economically at scale?

The answer increasingly depends on layers far beyond the accelerator itself: compute, memory, advanced packaging, interconnect, foundry capacity, and lithography. This week's developments—from ASML's High-NA EUV commitments to Nexperia's India partnership and Huawei's 2027 chip roadmap—make clear that the AI chip race is no longer a competition between individual processors. It is a competition between integrated systems.

The GPU Is Still Central—but No Longer Alone

GPUs remain the dominant force in AI compute. Bloomberg Intelligence projects that GPUs will capture 81% of the AI accelerator market by 2033, growing at a 14% compound annual rate to reach approximately $486 billion. Nvidia is expected to hold 70–75% of the AI accelerator market through 2030, with AMD positioned as the credible second source with a projected minimum 10% share by decade's end.

But custom silicon is gaining ground rapidly. The custom ASIC market is projected to expand at a 27% compound annual rate to reach $118 billion by 2033, growing from just 8% of the total market in 2024 to 19% by 2033. Broadcom commands 60–80% of the AI ASIC market through partnerships with Google, Meta, and OpenAI, while Marvell holds a 20–25% share through design wins with AWS and Microsoft.

The implication is not that GPUs are disappearing. It is that AI workloads are creating demand for a much broader semiconductor ecosystem—one in which general-purpose and specialized accelerators coexist, each optimized for different stages of the AI pipeline.

Custom Silicon Changes the Economics

Hyperscalers are increasingly designing or commissioning their own chips for strategic reasons: cost per inference, power efficiency, workload specialization, supply diversification, and reduced dependence on merchant GPUs. Google's TPU v7, Microsoft's Maia 200, Amazon's Trainium 3, and Meta's MTIA represent a collective bet that the economics of AI inference—the process of running trained models in production—are fundamentally different from training.

The Qualcomm–AWS partnership announced this month is the latest example. Qualcomm granted Amazon warrants tied to up to $60 billion in chip purchases over the next decade, with Amazon joining Microsoft and Meta as hyperscaler customers backing Qualcomm's data center push. The deal targets AI inference chips and includes optical connectivity solutions extending to 1.6 terabits per second. Qualcomm expects data center chip revenue to reach $15 billion by 2029.

The tradeoffs are real. Custom silicon requires significant development costs, software ecosystem investment, and manufacturing scale. But for hyperscalers spending tens of billions annually on AI infrastructure, the potential savings and strategic control justify the investment.

HBM and Advanced Packaging Become the Battlefield

As AI accelerators grow more powerful, the bottleneck is shifting from compute to memory and packaging. Every leading AI accelerator now depends on high-bandwidth memory (HBM), 2.5D packaging, advanced interposers, and high-bandwidth interconnects. The question the industry must answer: can chip performance continue improving if memory and packaging cannot keep up?

SK Hynix is positioning itself for this reality with a "Full-Stack AI Memory" strategy that goes beyond supplying memory devices to co-designing AI systems. Vice President Lim Eui-cheol described bundling 3D-stacked DRAM, HBM, and High-Bandwidth Flash (HBF) to match workload characteristics, while pursuing "system-level co-design" with AI services, software, and accelerator partners. The shift is driven by agentic AI workloads that require larger amounts of state information with varying lifespans and access characteristics—requirements that a single general-purpose memory cannot handle.

The HBM shortage has intensified dramatically. HBM4 prices are projected to rise from approximately $2 per gigabit to $4–5 or higher in the second half of 2026, driven by extreme manufacturing complexity and capacity constraints. Overall, DRAM and NAND prices have risen by 200–400% in some segments since the shortage began.

Advanced packaging has become an equally critical constraint. TSMC's CoWoS capacity is projected to reach 130,000–140,000 wafers per month by the end of 2026, up from approximately 70,000 in 2025, yet the supply-demand gap remains at roughly 20%. Nvidia alone has reserved approximately 800,000–850,000 wafers of TSMC's CoWoS capacity for 2026—more than 50% of the company's total capacity. The chiplet market is growing at a 66.7% compound annual rate, reaching $22.58 billion in 2026.

The Foundry Bottleneck

The semiconductor competition increasingly depends on access to advanced manufacturing rather than chip architecture alone. TSMC remains the dominant force: its 3nm monthly wafer starts are projected to reach 180,000 wafers by early Q4 2026, two to three months ahead of expectations, driven by orders from Nvidia, AMD, and Broadcom. Combined 2nm and 3nm monthly wafer starts could exceed 260,000 by early Q4.

Samsung and Intel are racing to close the gap. Samsung's Taylor, Texas, fab—a $37 billion investment—is reportedly fully booked for 2nm production before trial operations begin, with customers including Tesla, Broadcom, and Arm. Intel's 14A process is progressing, with PDK 0.9 expected in October 2026. But TSMC's scale advantage remains formidable: it holds approximately 72% of the global foundry market and more than 90% of advanced chips.

The strategic question is simple: who actually manufactures the chips that everyone else designs? For now, the answer is overwhelmingly TSMC.

Lithography Is Becoming More Strategic

The AI chip race ultimately runs through the equipment required to manufacture increasingly advanced chips. ASML's next-generation High-NA EUV systems—costing approximately $400 million each—can print features about 40% smaller than standard EUV tools. TSMC, Samsung, and SK Hynix have all set dates to begin using High-NA in production, while Intel, the early adopter, says the machines are already meeting throughput and reliability standards.

ASML's existing $200 million EUV machines are all but sold out through 2027, and CFO Roger Dassen described the customer mood as urgent: "Can you give me more? Can you give it to me fast?" JPMorgan estimates ASML held a 94% share of the global lithography market in 2025. The company broke ground on a new Eindhoven campus last week, signaling confidence that its dominance will extend into the 2030s.

The strategic implication is clear: the AI chip race ultimately runs through the equipment required to manufacture increasingly advanced chips. No amount of chip design innovation can compensate for a shortage of the tools that print the transistors.

Semiconductor Supply Chains Are Being Reconfigured

The Nexperia–Tata Electronics partnership announced on September 17 is a clear example of supply chain diversification in action. The agreement spans front-end wafer fabrication, back-end assembly and test, and technology collaboration, with Nexperia's MOSFET portfolio to be produced at Tata's upcoming 300mm fab in Dholera, Gujarat, and assembled at Tata's packaging facility in Jagiroad, Assam. Tata Electronics is building India's first commercial semiconductor fab and first indigenous assembly and test facility with a combined investment of $14 billion.

The partnership reflects broader efforts to reduce geographic concentration in semiconductor manufacturing—particularly Taiwan's dominance in advanced logic and packaging. India, Europe, and the United States are all investing heavily in domestic capacity, driven by government incentives and supply chain resilience concerns.

China and the Next Semiconductor Divide

China is accelerating its effort to build a domestic AI semiconductor stack. Huawei announced plans to launch two new AI chip lines in 2027—the 960DT series in Q1 and the Ascend 960PR in Q3—as part of a three-year strategy to compete with Nvidia. At the heart of Huawei's next-generation systems is UnifiedBus connectivity technology, designed to link large numbers of processors into a single computing system. The company has delivered more than 1,000 such systems to over 370 customers.

Huawei's Ascend 960 SuperPod combines UnifiedBus with the Hi-ONE optical system, enabling a cluster to connect up to 4,000 processors, with a longer-term goal of linking up to 100,000 Ascend chips in a single cluster. The company is also designing its own memory chips domestically and optimizing systems to overcome limitations. As Morgan Stanley analyst Charlie Chan noted: "Competition at the system level is more important than ever now."

What the Semiconductor Race Is Becoming

The layers are converging GPU → custom accelerator → HBM → advanced packaging → networking → foundry → lithography. The semiconductor industry is moving from a race between individual chips toward competition between integrated computing systems. Nvidia remains dominant, but its moat is increasingly defined by interconnect standards, software ecosystems, and supply chain relationships rather than raw compute performance alone.

What to Watch Next

1. Custom AI accelerator deployments as hyperscalers ramp their own silicon
2. HBM capacity and pricing as HBM4 ramps in 2027
3. Advanced packaging expansion beyond TSMC's CoWoS
4. TSMC, Samsung, and Intel process-node progress at 2nm and below
5. High-NA EUV adoption as TSMC begins production in 2030
6. Chiplet architectures and their impact on design economics
7. AI networking silicon from Marvell, Cisco, and Broadcom
8. Semiconductor supply-chain diversification in India, Europe, and the U.S.

The CODEW Take

The next semiconductor bottleneck may not be the chip itself. It may be everything required to manufacture, connect, cool, and feed that chip. The AI chip race is no longer a contest between GPUs. It is a systems race—and the winners will be those who control the full stack: memory, packaging, foundry capacity, lithography, and the geopolitical relationships that determine access to critical materials.

The CODEW Stat

The custom ASIC market is projected to grow at a 27% compound annual rate to reach $118 billion by 2033—growing from 8% to 19% of the total AI accelerator market—while GPUs still capture 81% of a $604 billion market. Meanwhile, TSMC's CoWoS advanced packaging capacity will reach 130,000–140,000 wafers per month by the end of 2026, yet the supply-demand gap remains at roughly 20%.

Sources

1. Reuters — "ASML extends chipmaking dominance as customers embrace High NA" (September 14, 2026)
2. Semiconductor Engineering — "Can GPUs Continue To Dominate AI Compute?"
3. Tech Insider — "Qualcomm-AWS $60B AI Chip Deal: Stock Jumps 7%" (September 2026)
4. Semiconductor Engineering — "Chip Industry Week in Review" (September 2026)
5. Reuters — "After fallout with Chinese parent, chipmaker Nexperia partners with India's Tata" (September 17, 2026)
6. The Indian Express — "China's Huawei sets 2027 launch for new AI chips as it targets Nvidia" (September 17, 2026)
7. Nexperia — "Nexperia and Tata Electronics announce strategic partnership" (September 17, 2026)
8. Bloomberg Intelligence — "AI Accelerator Market Looks Set to Exceed $600 Billion by 2033" (January 2026)
9. SK Hynix — "Full-Stack AI Memory" strategy presentation (September 9, 2026)
10. TrendForce — "TSMC 3nm Monthly Wafer Starts to Hit 180K by Early 4Q26" (August 2026)
11. TrendForce — "TSMC Reportedly Expands Outsourcing of Key CoWoS Front-End Step" (August 2026)
12. DigiTimes / 163.com — "HBM4 price to rise to $4-5 per gigabit in 2H 2026" (July 2026)

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THE CODEW · SEMICONDUCTOR WATCH

Editorial Note

Semiconductor Watch tracks the companies, technologies, manufacturing capacity, supply chains, and geopolitical forces shaping the global semiconductor industry—and explains how the chip ecosystem is evolving as AI becomes a major driver of demand. Each edition connects design → IP → fabrication → equipment → memory → packaging → interconnect → data-center deployment → supply chain → geopolitics.

Analysis is based on company disclosures, product developments, industry research, public reporting, and other publicly available information. Semiconductor demand, supply conditions, technology roadmaps, and geopolitical developments can change rapidly.