Semiconductor Watch: The AI Chip Race Moves Beyond GPUs
The AI Chip Race Moves Beyond GPUs
The AI Chip Race Moves Beyond GPUs
For the past three years, the semiconductor industry's AI narrative has been synonymous with Nvidia's GPU dominance. This week made clear that the next phase will be defined by something broader: a competitive ecosystem of accelerators, memory architectures, packaging technologies, and manufacturing capacity—all competing and collaborating to build the physical foundation of the AI economy.
The clearest signal came from d-Matrix, an AI inference chip startup that announced it will integrate its next-generation Raptor XPUs directly into Nvidia's rack-scale AI infrastructure using NVLink Fusion. But the week's developments also exposed the industry's most critical constraint: memory. Chinese AI chipmakers including Huawei and Cambricon have sharply raised prices—by as much as 50%—because the global HBM shortage has made memory the single most expensive component in an AI accelerator. Meanwhile, TSMC posted record August revenue of NT$514.8 billion, up 53.3% year-over-year, confirming that the demand for AI silicon remains insatiable. The semiconductor industry is no longer just selling chips. It is rationing the scarce resources—memory, packaging capacity, lithography tools—that determine how fast the AI buildout can proceed.
AI Accelerator Race
d-Matrix and the Rise of Specialized Inference Silicon
The d-Matrix collaboration with Nvidia is a milestone in the evolution of AI accelerators. The company's Raptor XPUs will plug directly into Nvidia's MGX rack architecture, using NVLink Fusion to connect with Vera CPUs, NVLink switches, BlueField-4 DPUs, and Spectrum-X Ethernet networking. The systems are expected to be available in 2027.
This is significant because it validates a thesis that has been building all year: AI inference—the process of running trained models in production—requires different silicon than AI training. Inference workloads are latency-sensitive, power-constrained, and increasingly agentic. d-Matrix's Raptor chips are purpose-built for ultra-low-latency inference, targeting applications like AI coding assistants, real-time chatbots, and voice agents.
Nvidia CEO Jensen Huang framed the partnership as a way to "expand accelerator choice" within the Nvidia ecosystem. The strategic logic is clear: by opening NVLink Fusion to specialized partners, Nvidia ensures that even as the accelerator market fragments, the interconnect layer remains unified under its control.
Broadcom's Custom Silicon Momentum
Broadcom's AI semiconductor revenue reached $16.7 billion in Q3 2026, up 221% year-over-year, with custom XPUs for Google, Anthropic, OpenAI, and Meta driving the surge. The company projects Q4 AI revenue of $21.7 billion and longer-term forecasts of roughly $115 billion in fiscal 2027 and $230 billion in fiscal 2028. Broadcom is no longer just a networking company—it is the primary beneficiary of hyperscalers' push to build their own chips.
HBM & Memory: The Strategic Bottleneck
China's AI Chipmakers Raise Prices as HBM Shortage Bites
The global HBM shortage is no longer a forecast—it is a present crisis. Huawei has raised the price of its Ascend 950DT accelerator to above 250,000 yuan ($37,255), a 20–50% increase from just two months ago. Cambricon has repriced its next-generation 690 chip 20–30% higher. Smaller rivals MetaX and Iluvatar CoreX have followed suit.
The root cause is simple: HBM accounts for a large share of an AI accelerator's production cost, and the global supply is dominated by SK Hynix, Samsung, and Micron. Since Washington tightened HBM export controls to China in December 2024, Chinese chipmakers have relied on grey-market channels, paying several times what buyers outside China pay.
The price hikes are reverberating through China's AI industry. ByteDance, which has been diversifying away from Nvidia, doubled its GPU shipments from Iluvatar CoreX to 100,000 units this year. Huawei's older Ascend chips have also risen in price—the 910C now sells for over 110,000 yuan, up from about 90,000 at the start of the year.
High-Bandwidth Flash: A New Memory Layer
The memory architecture itself is evolving. SK Hynix and SanDisk released the first open standard for High-Bandwidth Flash (HBF), a next-generation memory layer positioned between HBM and SSDs. HBF supports capacities up to 512GB with bandwidth grades ranging from 0.4TB/s to 3.0TB/s, using UCIe as the interconnect standard. HBF is designed to address a fundamental limitation of HBM: capacity. While HBM delivers extreme bandwidth, it is limited in how much data it can hold. HBF combines the bandwidth of HBM with the capacity of NAND flash, enabling AI inference devices to access larger models without moving data between memory tiers. Google and Tenstorrent are participating in the HBF consortium.
Advanced Packaging
Advanced packaging remains the tightest constraint in the AI chip supply chain. TSMC's CoWoS capacity for 2027 is fully booked, with some customers turning to Intel's EMIB-T as an alternative. The chiplet packaging market is growing at a CAGR of 42.5%, and ASE recently launched the 3DIC Advanced Manufacturing Alliance to standardize collaboration across Taiwan's supply base.
The strategic implication is clear: the AI chip race is no longer about transistor performance alone. The ability to combine logic, HBM, interconnects, and advanced packaging into a competitive system is becoming the defining competitive advantage.
Foundry & Manufacturing
TSMC's Record August Sales
TSMC reported August revenue of NT$514.8 billion ($16.35 billion), up 53.3% year-over-year and 10.1% sequentially—its fourth consecutive month of revenue growth. The company's 5nm, 4nm, and 3nm nodes are running at full capacity, driven by AI server chip demand. TSMC holds a 72.5% share of the global foundry market.
The numbers underscore a simple reality: the AI buildout is still accelerating. TSMC's Q3 revenue forecast of $44.6–$45.8 billion suggests no slowdown in demand.
ASML and the Next Generation of AI Chips
ASML is working with major chipmakers to adapt its High-NA EUV lithography tools for larger data center chips. Current High-NA tools use a smaller mask, which limits the maximum chip size. ASML plans to transition to 12-inch masks, enabling High-NA EUV to print chips as large as today's biggest data center processors. The productivity gain could be substantial: ASML CTO Marco Pieters estimates a 40% improvement in system productivity. A pilot line is planned for 2031, with high-volume production readiness by 2033. TSMC plans to adopt High-NA EUV for advanced-node production starting in 2030; Samsung targets 2028 for DRAM.
Semiconductor Geopolitics
Taiwan is flexing its chip diplomacy muscles. At SEMICON Taiwan, the government positioned the country as a "democratic and reliable supplier" of semiconductors for the AI era. Foreign Minister Lin Chia-lung highlighted opportunities in the chip supply chain, and Taiwan's companies signaled an additional $20 billion in planned U.S. investment.
But Taiwan is also facing pressure. The United States and European Union want Taiwanese chipmakers to expand local manufacturing. TSMC is already investing $265 billion in Arizona. Foxconn Chairman Young Liu said companies must now "think about how to manufacture with Taiwan, not in Taiwan—manufacturing with Taiwan in the countries where the markets are".
Meanwhile, China's anti-dumping measures against Japanese dichlorosilane—a chemical used to process silicon wafers—escalated a diplomatic dispute that began over Taiwan. The semiconductor supply chain is becoming a battleground for geopolitical competition.
What to Watch
- d-Matrix Raptor deployment timeline and whether other inference chip startups adopt NVLink Fusion.
- HBM pricing trends as the shortage intensifies and Chinese chipmakers pass costs to customers.
- TSMC's September revenue and whether the AI-driven demand trajectory continues.
- ASML's 12-inch mask progress and customer commitments for High-NA EUV.
- HBF adoption and whether Google's participation accelerates ecosystem momentum.
- China-Japan trade tensions and any further semiconductor-related retaliatory measures.
The next phase of the semiconductor race will not be won by the fastest GPU alone.
It will be determined by the ability to combine accelerators + HBM + advanced packaging + networking + manufacturing capacity + power efficiency into competitive AI systems. d-Matrix's integration into Nvidia's rack-scale ecosystem shows that specialized silicon can thrive alongside GPUs—but only within the interconnect and packaging frameworks that Nvidia controls.
The HBM shortage is the clearest evidence that memory has become the strategic bottleneck of the AI era. When Chinese chipmakers raise prices by 50% not because of design limitations but because they cannot secure enough memory, the industry's center of gravity has shifted.
The semiconductor industry is no longer just a technology industry. It is the strategic infrastructure of the AI economy—and the winners will be those who control the bottlenecks: memory, packaging, lithography, and the geopolitical relationships that determine access to critical materials.
The CODEW Stat
Huawei has raised the price of its Ascend 950DT accelerator by 20–50% to above 250,000 yuan ($37,255) in two months, while TSMC posted record August revenue of NT$514.8 billion, up 53.3% year-over-year—evidence that the AI chip race is now defined as much by memory scarcity as by compute performance.
Sources
- Reuters — Chip startup d-Matrix to use Nvidia chip-linking tech in AI servers
- d-Matrix — d-Matrix Adopts NVIDIA NVLink Fusion Rackscale Infrastructure
- Reuters — China's AI chipmakers raise prices as high-bandwidth memory shortage bites
- Barron's — TSMC Posts Record Sales
- Reuters — ASML to work with major chipmakers to use latest tools for larger chips
- Reuters — Taiwan flexes chip diplomacy muscles
- SK hynix — SK hynix Unveils First HBF Standard Specifications with Sandisk
Reviewed by Erwin Castro
on
Friday, September 11, 2026
Rating:
