Executive Intelligence · Special Report · November 7, 2026
The Global Semiconductor Power Shift: Who Controls the Future of Advanced Chip Manufacturing? — design, foundry, equipment, memory, advanced packaging, and the geopolitical forces reshaping who controls the industry.
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The Central Question — and Why the Conventional Answer Is Wrong
Ask who controls the global semiconductor industry, and the conventional answer is either Taiwan — because TSMC makes the most advanced chips — or the United States — because it designs them, writes the export rules, and hosts the largest AI chip companies. Both answers are incomplete. Power in semiconductors is not held by any single company or country. It is distributed across interdependent layers of the value chain—design, advanced wafer fabrication, lithography and process equipment, high-bandwidth memory, and advanced packaging—each with its own leaders, chokepoints, and geopolitical exposures. The AI demand surge has intensified concentration at the leading edge while accelerating diversification efforts and industrial policy responses.
This Special Report examines who actually controls the most strategically important segments of advanced chip manufacturing, how that balance is changing, and what the interdependence of the global semiconductor ecosystem means for the next five to ten years.
TSMC holds roughly 95% of leading-edge 3nm manufacturing and about 72% of the open foundry market. But it cannot make a single advanced chip without ASML, which holds a complete monopoly on EUV lithography and a 94% share of the overall lithography market. Nvidia dominates AI accelerator revenue at roughly 75%, but it cannot ship those accelerators without SK hynix — which supplies an estimated 70–90% of Nvidia’s HBM — or without CoWoS advanced packaging, where TSMC is again the primary supplier. And every one of those layers is now being reshaped by export controls that have produced an outcome opposite to their intent: China’s advanced chip output is rising, its domestic equipment makers are climbing global rankings, and its memory manufacturers are within one to three years of the incumbents.
Editorial Note: This report distinguishes technology leadership, manufacturing scale, market share and strategic control throughout. They are not interchangeable. Market-share figures are attributed to their sources and carry the usual caveats about methodology. Announced capacity, investment targets and customer evaluations are not treated as completed manufacturing output. Forecasts and estimates are labelled as such.
1. Design — The Companies That Specify the Chip
Semiconductor design is the most visible layer of power and the least structurally secure. The companies here own the architecture, the instruction set and — in Nvidia’s case — the software ecosystem that makes the hardware usable. But design firms are overwhelmingly fabless: they depend on someone else to manufacture what they specify.
Nvidia remains the dominant force in AI accelerators, with an estimated 75% of AI accelerator revenue in 2026, down from a peak near 87% in 2024. Its data-center revenue reached $89.0 billion in the quarter ended July 26, 2026, up 117% year over year, and its guidance for the following quarter was $108 billion — with no data-center compute revenue from China assumed. The moat is not the GPU alone; it is CUDA, the software platform that has held AI developers for more than a decade. Nvidia’s CEO has said the company has visibility to $1 trillion in Blackwell and Vera Rubin sales from 2025 through calendar 2027.
Broadcom is the quiet counterweight. Its AI semiconductor revenue reached $16.7 billion in the quarter ended August 2, 2026, up 221% year over year, and it captured roughly 73% of AI chip revenue from custom ASIC programmes for customers including Google, Meta and Anthropic. Broadcom does not sell a branded accelerator; it designs the chips that hyperscalers commission so they do not have to buy Nvidia’s. That makes it the principal beneficiary of every company that wants an alternative to CUDA — and the principal threat to Nvidia’s pricing power.
AMD is the third force. Its data-center segment generated $6.718 billion in the quarter ended June 27, 2026, up 107% — a figure that includes server CPUs as well as AI GPUs. AMD’s advantage is not peak performance but total cost of ownership for inference and mixed workloads, and its Helios rack-scale platform positions it to compete for the systems business that Nvidia has dominated.
Arm Holdings sits underneath much of this competition. Its data-center royalties doubled year over year in fiscal Q2 2027, and licensing revenue reached $773 million. Arm’s position is structurally different: it does not compete with its customers; it licenses the instruction set they build on. But its own ambitions in chip design have complicated that neutrality.
China’s design ecosystem — Huawei/HiSilicon, Alibaba T-Head, Baidu Kunlunxin, Cambricon — is growing under the protection of export controls. The critical constraint is not design capability but manufacturing access: these companies can specify competitive chips, but they depend on SMIC’s advanced nodes, which remain years behind TSMC in yield and cost.
The design-layer verdict
The United States controls design — but not exclusively. Nvidia leads merchant AI accelerators; Broadcom leads custom ASICs; Arm licenses the architecture beneath both. China’s design firms are credible but manufacturing-constrained. Design leadership is American, but it is dependent on Taiwanese manufacturing and Dutch lithography.
2. Foundry — Who Can Actually Make the Most Advanced Chips
The foundry layer is where the popular narrative of TSMC dominance is both correct and misleading. TSMC holds approximately 72% of the open foundry market and more than 90% of advanced chips, depending on how “advanced” is defined. But the more revealing figure is at the leading edge: in the 3nm class, TSMC holds an estimated 95% share.
Samsung Foundry is the only credible near-term alternative, and the gap remains wide. Samsung held 5.9% of the global foundry market in Q2 2026, against TSMC’s 72.5%. Its SF2 (2nm) yield has climbed from about 30% in mid-2025 to nearly 60% — a meaningful improvement that makes the process commercially viable, though still below TSMC’sæç yields. Samsung is expected to supply 2nm chips to Tesla, and its SF2P second-generation process promises 12% higher performance and 25% lower power.
Intel Foundry is the most consequential variable in the foundry equation. Its 18A process is ramping, with yields improving 7–8% per month, and KeyBanc analysts report that Intel has secured contracts from Broadcom, Google, Apple, AMD, Microsoft, and Nvidia for its 18A-P and 14A processes. Apple’s orders alone could represent 600,000 wafers on Intel’s 14A, worth an estimated $15–20 billion. Tesla has selected Intel’s 14A for its Terafab project. If those contracts convert to volume, Intel becomes the first credible third source at the leading edge since Samsung’s early 5nm efforts.
SMIC, China’s largest foundry, illustrates the limits of the export-control strategy. It reported record revenue of $9.33 billion for its latest full financial year, up 16.2%, and maintained 93.7% capacity utilisation. But that revenue rests on mature nodes, not leading-edge. SMIC’s 7nm process uses quadruple-patterning DUV — dividing circuit layouts into four separate exposures — and commercial yields hover between 20% and 30%, pushing per-wafer costs 40–50% above TSMC’s equivalent processes. It is producing 7nm and “5nm-class” chips, but not at commercially competitive cost or volume.
| Company | Leading-edge status | Strategic position |
|---|---|---|
| TSMC | ~95% of 3nm; 2nm ramping | Indispensable at the leading edge |
| Samsung | SF2 yield ~60%; 5.9% foundry share | Credible alternative, still distant |
| Intel | 18A ramping; 14A contracted | Potential third source — unproven at volume |
| SMIC | 7nm yields 20–30%; 5nm-class | Mature-node scale; leading-edge constrained |
The foundry-layer verdict
Taiwan controls leading-edge manufacturing, and no alternative is close at the 3nm class. But the transition to 2nm is the inflection point. If Intel’s contracted customers convert to volume and Samsung’s yield continues to improve, the foundry layer becomes less concentrated over the next five years. If neither executes, TSMC’s position becomes more entrenched, not less.
3. Equipment — The Industry’s Most Powerful Gatekeepers
If you want to identify the single most powerful company in the semiconductor industry, the answer is not TSMC or Nvidia. It is ASML. The Dutch equipment maker holds a complete monopoly on EUV lithography — the technology required to print the finest features on advanced AI chips — and a 94% share of the global lithography market. Every advanced logic and memory chip in the world depends on its machines. Each current-generation EUV system costs roughly $200 million, and each next-generation High-NA EUV system costs approximately $400 million. ASML’s order book is effectively full through 2027, and it plans to raise EUV output to 90 systems in 2026.
The rest of the equipment layer is competitive but concentrated. Applied Materials, Lam Research, KLA and Tokyo Electron dominate deposition, etch, inspection and metrology respectively. Nikon and Canon remain in lithography but have been marginalised at the leading edge.
China’s equipment makers are the most under-reported development in the industry. Naura Technology rose from eighth place in the global equipment sales rankings in 2022 to fifth in 2025, trailing only ASML and the other Western incumbents. AMEC entered the global top 20 at 13th place. TSMC’s Nanjing fab has reportedly placed orders with AMEC for 5nm dielectric etching tools — a remarkable validation for a Chinese equipment vendor. Naura has also developed hybrid bonding tools for advanced packaging, placing it among the first in China to complete customer-side verification for die-to-wafer bonding.
The equipment layer is where export controls bite hardest. SMIC cannot buy EUV from ASML, and licensing curbs on advanced immersion DUV scanners restrict its access to the tools needed for advanced nodes. But the controls have also accelerated domestic substitution: SMIC integrates etching and deposition equipment from Naura and Piotech to replace Western hardware, and Chinese firms are developing alternative patterning approaches. Domestic lithography tools remain years away from commercially matching imported immersion scanners, but the direction is clear.
The equipment-layer verdict
The Netherlands controls the single most irreplaceable input in the semiconductor supply chain. ASML’s monopoly is the strongest strategic position in the industry — stronger than TSMC’s foundry share, because there is no alternative at all. China’s equipment makers are climbing fast in etch, deposition and packaging, but lithography remains the gap that export controls were designed to preserve.
4. Memory — The AI Infrastructure Supply Chain
High Bandwidth Memory (HBM) is the component that determines how fast an AI accelerator can be fed data. It is also one of the most concentrated parts of the supply chain. SK hynix holds roughly 50–56% of the HBM market, and it supplied an estimated 70–90% of Nvidia’s HBM through 2025 on a receipts basis. Samsung and Micron are roughly tied for second at around 18–21% each, though Samsung leads the broader DRAM market with a 38% share against SK hynix’s 25%.
The concentration is structural. Nvidia alone consumes roughly two-thirds of total HBM industry output. That gives the memory makers enormous leverage over accelerator pricing, and it gives Nvidia a strong incentive to qualify multiple suppliers — which is why Samsung and Micron are gaining share as they ramp production.
China’s memory challengers are closer than most industry observers expected. The Korea Semiconductor Industry Association puts the technology gap at three years in HBM, two years in DRAM, and one year in NAND flash — down from roughly five years not long ago. YMTC has completed 294-layer 3D NAND and plans trial production of LPDDR5 DRAM by the end of 2026. CXMT is ramping DRAM capacity from around 320,000 wafers per month toward higher volumes, and it is preparing an HBM-focused capacity of approximately 50,000 wafers per month by the end of 2026, though its HBM3E yields are reported at only about 25%. Both companies are pursuing a distinctive strategy: using YMTC’s X-Stacking hybrid bonding to build HBM stacks without EUV lithography.
The memory-layer verdict
South Korea controls HBM today, and the United States has one credible challenger in Micron. China’s memory makers are narrowing the gap faster than the equipment controls were designed to allow, and they are doing it without EUV. The HBM lead is a South Korean asset, but it is not a permanent one.
5. Advanced Packaging — The New Battleground
For two years, the AI chip narrative centred on a single question: can foundries make enough wafers? In 2026, the constraint has extended downstream. Revenue from advanced packaging is forecast to overtake revenue from traditional packaging for the first time in 2026, with capital spending on the technology expected to approach $28 billion. Former Intel CEO Pat Gelsinger has estimated that advanced packaging could eventually account for as much as half the value of a chip product, as some processors integrate ten or more chips.
TSMC dominates CoWoS — Chip-on-Wafer-on-Substrate — the technology that links processors and HBM on a shared base so they can work together at high speed. It is used by Nvidia, AMD, Broadcom and cloud companies developing their own AI chips. TSMC’s CoWoS capacity is projected to rise from approximately 70,000 wafers per month in 2025 to 130,000–140,000 by the end of 2026, and total CoWoS wafer output is estimated to grow from 106,000 units in 2026 to 227,000 units in 2027. Even so, demand continues to outstrip supply.
The capacity constraint has created an opening for alternatives. Nvidia is providing billions of dollars in financing to expand CoWoS packaging capacity at Siliconware Precision Industries (SPIL), a unit of Taiwan’s ASE Technology — funding that supports new factory space and equipment, and a scale of support that has not previously been reported. Amkor Technology, Powertech Technology and Intel are also investing in advanced packaging. Intel’s EMIB-T technology is reportedly in line to earn between $12 billion and $15 billion on Google’s TPU programmes.
Advanced packaging is becoming strategically important because it is where heterogeneous integration happens. A leading-edge AI accelerator is no longer a single die; it is a package containing multiple compute chiplets, HBM stacks, and sometimes networking or I/O dies. Whoever controls the packaging technology controls how those components are assembled — and therefore how much performance can be extracted from the silicon inside them.
The packaging-layer verdict
Taiwan controls advanced packaging through TSMC and ASE, and that control is becoming as strategically important as leading-edge wafer fabrication. The difference is that packaging capacity is easier to expand than lithography, and alternatives exist. The packaging layer is likely to become less concentrated than the foundry layer over the next three years.
6. Geopolitics — Export Controls and the Paradox of Protection
The United States’ export-control strategy rests on a straightforward premise: deny China access to EUV lithography and high-performance GPUs, and China’s technological progress will hit a wall. In 2026, that premise is showing its limits.
The controls have slowed China’s entry into advanced nodes — SMIC’s 7nm yields and costs confirm that. But they have also produced a paradox of protection. By blocking Nvidia’s high-end GPUs, the controls created a captive domestic market for Huawei’s Ascend accelerators and for Chinese software ecosystems such as Huawei’s CANN, which competes with CUDA. Chinese AI developers that might have defaulted to Nvidia’s ecosystem have been forced to build alternatives, and they have had time to do so. As one analysis puts it: architecture is beginning to win over physics — China is finding workarounds through software optimisation, chip stacking and system-level design rather than through sheer lithographic scaling.
The controls are also leaky. Despite restrictions, China has obtained hundreds of immersion DUV lithography systems that can be used for advanced chip manufacturing — enough that a U.S. research group has warned the AI chip competitiveness of the United States and its allies could weaken or disappear within five to ten years if the flow continues. Congress has pushed for tighter controls, but the cat is partly out of the bag.
Meanwhile, every major economy is subsidising domestic capacity. TSMC’s Arizona fab is in production, with output projected to rise 1.8× year over year in 2026; its second Arizona fab is installing tools; its Japan fab is producing 22nm and 28nm; its Germany fab is under construction. TSMC has received government subsidies from the US, Japan, Germany and China, including 25% investment subsidies for qualifying Arizona investments. Intel is rebuilding its foundry business with a similar logic, and Samsung is anchoring its Taylor, Texas fab to foundry profitability.
The result is a semiconductor map that is less globalised and more redundant than it was five years ago. That redundancy is expensive — TSMC’s Arizona fabs cost more to build and operate than its Taiwan fabs — but it is also a hedge against the geographic concentration that made the 2021 chip shortage so severe.
The geopolitical verdict
The United States can slow China’s progress at the leading edge, but it cannot stop China from building a parallel ecosystem. The controls have accelerated domestic substitution in equipment, memory and design. Over five to ten years, the most likely outcome is not Chinese dominance but a bifurcated supply chain — one Western-aligned, one Chinese-aligned, with limited interchange at the leading edge.
Comparative Assessment — Power Across the Value Chain
| Layer | Technology leader | Manufacturing scale | Strategic control |
|---|---|---|---|
| Design | US (Nvidia, Broadcom, AMD, Arm) | US (fabless scale) | US — architecture, EDA, software ecosystems |
| Foundry | Taiwan (TSMC) | Taiwan (TSMC), South Korea (Samsung) | Taiwan — leading-edge concentration |
| Equipment | Netherlands (ASML), US (AMAT, Lam, KLA), Japan (TEL) | US, Japan, Netherlands | Netherlands — EUV monopoly; US — export-control chokepoint |
| Memory | South Korea (SK hynix, Samsung) | South Korea, US (Micron) | South Korea — HBM leadership; China closing |
| Advanced packaging | Taiwan (TSMC CoWoS, ASE) | Taiwan, US (Amkor), Intel | Taiwan — CoWoS bottleneck |
| Geopolitics | — | US, China, EU, Japan, South Korea | US — export controls, subsidies; China — domestic substitution |
Source: The CODEW assessment based on company filings, industry research and reporting cited throughout. Technology leadership, manufacturing scale and strategic control are distinct dimensions and are not combined into a single ranking.
There is no single winner in the semiconductor industry, and the search for one is the wrong question.
The United States leads in design, software ecosystems and export-control leverage. Taiwan leads in leading-edge foundry and advanced packaging. The Netherlands holds an absolute monopoly on the single most irreplaceable piece of equipment. South Korea leads in HBM. Japan and the United States dominate the broader equipment layer. China is building a parallel ecosystem at every layer, slower at the leading edge but faster than most expected. Each of these positions is a form of power, and none of them is sufficient on its own.
The industry’s defining characteristic is interdependence, not hierarchy. Nvidia cannot ship without TSMC and SK hynix. TSMC cannot operate without ASML. ASML cannot sell without the permission of the Dutch and U.S. governments. China cannot build a leading-edge foundry without equipment it is not allowed to buy — but it can build a mature-node business that is large, profitable and increasingly self-sufficient. Every actor in the chain holds leverage over every other actor, and every actor is vulnerable to the one below it.
The next five years will be defined by three transitions, and each will redistribute power:
First, the 2nm transition. TSMC is the incumbent, but Samsung’s yield is improving and Intel has won contracts from the companies that matter. If Intel converts those contracts to volume, the foundry layer becomes a three-way race for the first time in a decade. If it does not, TSMC’s position hardens.
Second, the packaging transition. Advanced packaging is becoming as strategic as wafer fabrication, and the capacity constraint is real. Nvidia is already funding ASE’s expansion because it cannot get enough CoWoS from TSMC. If packaging becomes the primary bottleneck in AI accelerator supply, the companies that control packaging capacity — TSMC, ASE, Amkor, Intel — gain leverage relative to the designers.
Third, the China transition. The export controls have not stopped China; they have redirected it. SMIC’s leading-edge yields are poor, but its mature-node business is strong and its equipment makers are climbing global rankings. YMTC and CXMT are within one to three years of the memory incumbents. The most likely outcome is not Chinese dominance but a durable bifurcation: a Western supply chain and a Chinese supply chain, each with its own strengths and weaknesses, competing for influence over the standards, customers and talent in the rest of the world.
The strategic implication for governments and companies is uncomfortable. No country can achieve full semiconductor self-sufficiency at the leading edge — not the United States, not China, not the EU. The best available strategy is not independence but positioning at the layers where you have irreplaceable leverage, and building redundancy at the layers where you are dependent. The Netherlands has done this with ASML. Taiwan has done it with TSMC. South Korea has done it with HBM. The United States has done it with design and export controls. China is trying to do it across the board, and succeeding faster at some layers than others.
The caveat worth stating plainly: this report rests on company filings, industry research, and credible reporting. Market-share figures vary by methodology and quarter; the figures cited are indicative of concentration, not definitive rankings. Intel’s contracted customers, Samsung’s yield improvements, China’s memory progress and TSMC’s capacity plans are all company-reported or analyst-estimated and are not independently verified. Announced capacity and investment targets are not completed output. The strategic read is defensible; the outcomes are not yet established.
The CODEW Stat
Six layers. Six gatekeepers. Zero monopolies at the system level. TSMC’s 95% share of 3nm manufacturing is the highest concentration in any layer — but it is a concentration of manufacturing, not of control. TSMC depends on ASML for lithography, on Applied Materials, Lam and TEL for deposition and etch, on Shin-Etsu and SUMCO for wafers, and on the U.S. government for export licences. ASML depends on TSMC, Samsung and Intel for revenue, and on the Dutch and U.S. governments for export permissions. Nvidia depends on TSMC, SK hynix and CoWoS. The semiconductor industry is not a hierarchy with a single apex. It is a network in which every node holds leverage over every other node, and every node is vulnerable.
Sources & References
- Nvidia — Q4 FY2026 and Q1 FY2027 results; data-center revenue $62.3B and $89.0B; $1T Blackwell/Rubin visibility — investor.nvidia.com
- AI chip market share 2026 — Nvidia ~75% of AI accelerator revenue; Broadcom $16.7B AI semiconductor revenue (+221%); AMD $6.718B data-center revenue — safeguard.sh
- EE Times — “Three Misconceptions About the $402B Semiconductor Foundry Industry”; TSMC ~95% of 3nm, ~72% open foundry, ~34% total manufacturing — eetimes.com
- Samsung 2nm yield — SF2 yield near 60%; foundry share 5.9% vs TSMC 72.5% — electronicsforyou.biz
- Intel Foundry contracts — KeyBanc: Broadcom, Google, Apple, AMD, Microsoft, Nvidia; Tesla selects 14A — wccftech.com
- SMIC — record $9.33B revenue; 7nm yields 20–30%; costs 40–50% above TSMC; 93.7% utilisation — eastasiabrief.com
- ASML — 94% lithography share (JPMorgan); EUV monopoly; $200M/$400M tool costs; order book through 2027 — cna.com.tw, electronicsforyou.biz
- China equipment makers — Naura #5 globally; AMEC #13; TSMC Nanjing orders 5nm etch tools — trendforce.com, chinadaily.com.cn
- HBM market share — SK hynix 50–56%; Samsung/Micron ~18–21%; SK hynix 70–90% of Nvidia HBM — safeguard.sh, eastasiabrief.com
- China memory gap — YMTC 1 year behind on NAND; CXMT 2 years on DRAM, 3 on HBM; CXMT HBM3E yield ~25% — wccftech.com, trendforce.com
- Advanced packaging — Reuters: revenue overtaking traditional in 2026; ~$28B capex; TSMC CoWoS 70k→130–140k wafers/month; Nvidia funding SPIL — reuters.com
- Export controls paradox — China’s CANN/DeepSeek ecosystem; “architecture wins over physics”; hundreds of immersion DUV systems obtained — csf.kiep.go.kr, rti.org.tw
- TSMC global fabs — Arizona output 1.8× in 2026; Japan 22/28nm volume; Germany under construction; government subsidies including 25% Arizona investment — electronicsweekly.com, taiwannews.com.tw
- Semiconductor capex — TSMC 2026 capex $46–48B (Citi estimate, potential to $50B); memory capex +67% to $97B in 2026, +50% to $146B in 2027 (Deloitte) — sina.com.cn, nai500.com
Market-share figures are drawn from multiple research sources and vary by methodology, definition and quarter. The figures cited are indicative of concentration, not definitive rankings. Announced capacity, investment targets and customer evaluations are not treated as completed manufacturing output. Intel’s contracted customers, Samsung’s yield improvements, China’s memory progress and TSMC’s capacity plans are company-reported or analyst-estimated and are not independently verified. Forecasts are labelled as such. This report does not provide investment advice.
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