Semiconductor Watch: Memory Chip Shortage, China's Chip Push
AI Memory Demand, China's Chip Push and the Race to Expand Global Capacity
Memory Becomes the Strategic Bottleneck of the AI Economy
The semiconductor industry's center of gravity is shifting decisively toward memory. This week, China's CXMT announced that its fifth-generation DRAM platform has entered mass production, claiming a feature spacing of 11.95 nanometers achieved without access to the advanced lithography tools it is barred from importing. The same company is preparing to enter NAND flash, putting it into direct competition with Samsung, SK Hynix, Micron, and China's own YMTC.
Meanwhile, the AI-driven memory shortage is intensifying. TrendForce data shows DRAM contract prices rose roughly 90–95% in Q1 2026, another 58–63% in Q2, and are on track for a further 13–18% increase in Q3. UBS now attributes nearly 90% of its upward revision to 2026 AI capital expenditure—now approaching $1 trillion—to the rising cost of DRAM and HBM. The bottleneck in AI infrastructure is shifting from GPUs to memory. Against this backdrop, the United States is racing to build domestic memory capacity. The common thread: the semiconductor industry is entering a memory-centric phase of the AI buildout—and the geographic, technological, and supply-chain dynamics of memory are becoming as strategically important as the GPU itself.
CXMT's G5 DRAM Platform Enters Mass Production
China's ChangXin Memory Technologies (CXMT) announced on September 20 that its fifth-generation DRAM platform, known as the G5 platform, has entered mass production. The announcement was made at the 2026 World Manufacturing Convention in Hefei.
Key technical details:
- Feature spacing: The G5 platform achieves an active area half-pitch of 11.95 nanometers for memory arrays, using innovative quadruple patterning (SAQP) technology.
- Density improvement: The number of dies produced per wafer rises by at least 50% compared with the previous generation.
- Products: CXMT showcased two LPDDR5X products based on the G5 platform, both featuring 24Gb capacity—50% higher than comparable previous-generation products.
- Applications: The products use 496-ball and 245-ball packaging and are designed for mid-to-high-end smartphones and portable consumer electronics.
The significance of the 11.95nm figure is that CXMT achieved this feature spacing without access to extreme ultraviolet (EUV) lithography, which China is barred from importing. The company used quadruple patterning—a more complex, lower-yield approach than EUV—to push conventional DUV lithography to its limits. CXMT also reported progress in interface engineering, saddle-fin structures, and low-k spacer bitlines, and it built a digital-twin system covering the full product lifecycle from design to manufacturing.
Ma Jihua, a veteran telecom industry analyst, told the Global Times that the global DRAM market remains dominated by Samsung, SK Hynix, and Micron, making technological advances by additional players closely watched. He noted that advances in high-end memory technologies could strengthen China's indigenous innovation and provide downstream manufacturers with more sourcing options.
TrendForce reported that global DRAM industry revenue jumped 59.5% quarter-on-quarter in Q2 2026, while supply expansion continued to lag demand growth.
The CODEW take: CXMT's G5 platform represents a meaningful technology step, but it should be assessed in context. The company is not yet competing at the leading edge of HBM or DDR5 server memory, where Samsung, SK Hynix, and Micron retain dominant positions. However, in conventional DRAM—the memory used in smartphones, PCs, and consumer electronics—CXMT is filling a vacuum left by the major suppliers' pivot toward high-value AI memory. As the big three prioritize HBM and advanced server DRAM, CXMT is capturing share in the mainstream and legacy segments. That dynamic could give the company a durable foothold in the global memory market.
China's Memory Ambitions Expand Beyond DRAM
CXMT is preparing to enter the NAND flash market, according to reporting from Reuters. The company plans to establish a research-and-development production line for NAND flash memory at its new plant in Beijing and has set up a research institute in the Chinese capital focused on NAND development.
This move would pit CXMT against Samsung (the world's biggest NAND supplier with a 29.3% revenue share in Q2), SK Hynix, Micron, and its domestic rival YMTC. CXMT and YMTC are known in China as the "twin stars" of the country's memory-chip industry, and the two have largely operated in separate markets—CXMT dominating Chinese DRAM production and YMTC focusing on NAND. CXMT's entry into NAND would bring them into direct competition.
The context for this expansion is the global memory shortage. Strong demand from AI servers has created a shortage that industry executives believe will persist through at least 2027. SK Hynix CEO Kwak Noh-jung said in July that 2027 could be the industry's worst year from a supply perspective, while TrendForce expects NAND supply tightness to ease only in the second half of next year.
Manufacturers have prioritized capital spending on DRAM and HBM, limiting additions to NAND flash capacity. TrendForce noted that this is worsening shortages in the NAND segment. CXMT has already demonstrated pricing power: the company was reportedly charging more than Samsung for 64GB DDR5 server modules in July.
The CODEW take: China's memory strategy is no longer just about import substitution. CXMT's NAND ambitions signal that China intends to compete across the entire memory stack—DRAM, NAND, and eventually HBM. The global shortage has given Chinese suppliers an unusual window of pricing power and customer access. Whether they can convert that window into durable market share depends on manufacturing yields, equipment access, and the willingness of global customers to source from Chinese suppliers.
The AI Boom Is Reshaping Semiconductor Capacity
The memory shortage is not a temporary imbalance—it is a structural feature of the AI infrastructure buildout. KB Securities, analyzing the AI Infra Summit 2026 held in Santa Clara, reported that the critical bottleneck in AI infrastructure is shifting from GPUs to memory.
Why memory is the bottleneck:
- HBM cannibalizes DRAM capacity: Every wafer devoted to HBM displaces roughly three wafers of conventional DRAM capacity. As AI accelerators require ever-larger HBM stacks, general-purpose DRAM supply tightens.
- Agentic AI demands more memory bandwidth: Conversational AI operates at around 100 tokens per second; agentic AI environments require 10 times higher performance at 1,000 tokens per second. System performance determinants are shifting from computational power to memory bandwidth and data supply speed.
- New supply takes years: A new memory fab takes roughly three years to build and ramp. SK Hynix's first Yongin fab and Micron's first new Idaho fab are not expected to meaningfully add output until mid-to-late 2027. Samsung's P5 fab is a 2028 story. IDC expects 2026 supply growth of only about 16% for DRAM and 17% for NAND—well below what AI demand requires.
The pricing reality: Regular DRAM contract prices jumped about 90–95% in Q1 2026, another 58–63% in Q2, and are on track for a further 13–18% increase in Q3. A DRAM chip that cost $1 in January costs roughly $3.50 today. NAND flash is up about 3x over the same stretch. HBM spot prices are running at roughly four to five times long-term contract levels.
UBS raised its 2026 AI capital expenditure forecast to $998 billion, attributing nearly all of the increase to the rising cost of DRAM and HBM. The bank noted that HBM pricing has been the tightest link in the AI supply chain because the packaging step—stacking DRAM dies and bonding them to a logic interposer through TSMC's CoWoS process—limits how many accelerators can ship regardless of how much leading-edge logic capacity exists.
The CODEW take: Memory is no longer a component of AI infrastructure—it is becoming the constraint. The industry's ability to expand HBM, DRAM, and NAND capacity will determine how fast AI systems can be deployed. This is a multi-year problem with no quick fix. Enterprises planning AI infrastructure investments should assume memory pricing pressure and supply constraints through 2027 at minimum.
U.S. Manufacturing Becomes Part of the Memory Story
SK Hynix–Intel Talks
SK Hynix is in early talks with Intel about manufacturing memory chips on U.S. soil for the first time. Options under discussion include leasing part of Intel's Ohio facility or forming a joint venture involving Intel and major cloud companies seeking to secure memory supply. Intel's Ohio complex, launched in 2022 with a planned investment of up to $100 billion, was originally scheduled to begin production in 2025 but has been delayed to at least 2030. A partnership with SK Hynix could provide additional utilization for the facility amid those delays.
Shares of both companies jumped on the news, with Intel up 9% on September 17. However, the talks remain exploratory, and no agreement has been finalized. One potential obstacle is approval from the South Korean government: if the agreement involves advanced memory technologies like HBM or DRAM, it could be subject to review under the Industrial Technology Protection Act.
SK Hynix is already developing a $4 billion facility in Indiana for advanced HBM packaging and R&D, with volume production of next-generation HBM4E chips expected to begin in 2029.
Solidigm's U.S. NAND Factory
SK Hynix's U.S. subsidiary Solidigm is considering building a NAND flash memory factory in the United States, with upstate New York emerging as a leading candidate for the site. Solidigm currently operates a plant in Dalian, China, and has only its headquarters and R&D center in the United States. A U.S. manufacturing facility would give Solidigm an additional source of NAND production and reduce its reliance on its existing China-based facility. It could also help the company limit exposure to potential U.S. tariffs and restrictions on semiconductor manufacturing equipment exports to China. The proposed factory would be separate from the SK Hynix–Intel discussions.
The CODEW take: The U.S. is making progress in attracting memory manufacturing, but the timelines are long and the obstacles are significant. Intel's Ohio facility is years behind schedule. Korean government approval may be required for advanced memory technology transfers. And U.S. manufacturing costs are significantly higher than in South Korea or China. The strategic intent is clear—reduce dependence on Asian memory supply—but the execution will take years, if not decades.
Equipment Remains a Critical Bottleneck
ASML's High-NA EUV lithography systems are being adopted across the industry, and the memory makers are setting aggressive timelines.
Adoption timelines:
- Samsung: Plans to introduce High-NA EUV for high-volume DRAM production by 2028. Samsung has been working closely with ASML on next-generation lithography, bringing South Korea's first High-NA EUV system in March 2025.
- SK Hynix: Similarly targeting 2028 for mass production applications in DRAM, and is considering joining the Large Size Mask Consortium led by TSMC.
- TSMC: Plans to deploy High-NA for advanced logic production starting in 2030.
- Intel: Already using High-NA for its Panther Lake processors, the early adopter among the major chipmakers.
Why High-NA matters for memory: High-NA EUV uses a higher numerical aperture (0.55 vs. 0.33 for conventional EUV), improving resolution and reducing the number of multipatterning steps. Conventional EUV requires four multipatterning steps to achieve 2nm-class features; High-NA EUV could theoretically cut the number of process steps in half, significantly lowering manufacturing costs.
The technology is also seen as critical for maintaining a technology lead over China's rapidly advancing memory capabilities. As China begins limited production of HBM3E despite EUV restrictions, Samsung and SK Hynix's push to adopt High-NA EUV could be crucial to maintaining a significant technology lead in advanced DRAM and HBM. ASML also announced collaborations with TSMC, Samsung, SK Hynix, and Intel to drive the transition from today's 6-inch photomasks to larger 12-inch masks for High-NA EUV systems.
The CODEW take: Equipment remains the ultimate bottleneck in the semiconductor supply chain. Without ASML's High-NA EUV tools, advanced memory and logic production cannot scale. The memory makers' 2028 timelines for High-NA adoption in DRAM signal that the next generation of memory technology—critical for AI workloads—depends on equipment that is currently sold out through 2027.
The semiconductor industry is entering a memory-centric phase of the AI buildout.
Three dynamics are converging:
1. Memory is becoming the binding constraint on AI infrastructure. The shift from conversational AI to agentic AI—systems that autonomously reason, call tools, and execute multi-step tasks—is driving a 10x increase in memory bandwidth requirements. HBM capacity is cannibalizing conventional DRAM production. New fabs take three years to build. The industry cannot expand memory capacity fast enough to meet demand, and the shortage is expected to persist through at least 2027.
2. China is building a full-stack memory capability. CXMT's G5 DRAM platform entering mass production is a significant technology milestone achieved without EUV access. The company's planned entry into NAND flash would make it a competitor across the memory stack. China's strategy is not just about self-sufficiency—it is about becoming a global supplier in a shortage-constrained market where customers are desperate for alternatives.
3. The U.S. is trying to onshore memory manufacturing, but the timelines are long. SK Hynix's talks with Intel, Solidigm's NAND factory consideration, and the Indiana HBM packaging plant are all steps in the right direction. But Intel's Ohio facility is delayed to at least 2030. Korean government approval may be required for advanced technology transfers. And U.S. manufacturing costs remain significantly higher than in Asia.
The strategic question for the industry: Can memory capacity expand fast enough to support the AI buildout? The answer depends on three factors: how quickly new fabs can be built and ramped, how effectively High-NA EUV adoption accelerates advanced memory production, and whether Chinese suppliers can scale to fill the gap in conventional DRAM and NAND.
What to Watch
- HBM supply and pricing as HBM4 ramps and Samsung, SK Hynix, and Micron compete for AI accelerator design wins.
- DRAM and NAND contract pricing in Q4 2026 and Q1 2027 as the shortage trajectory becomes clearer.
- CXMT's G5 platform yields and customer adoption in mainstream DRAM segments.
- CXMT's NAND plans and whether the company moves from R&D to commercial production.
- SK Hynix–Intel talks and whether a deal is reached—and under what terms.
- Solidigm's U.S. NAND factory decision and site selection.
- ASML High-NA EUV adoption as Samsung and SK Hynix target 2028 for DRAM mass production.
- Samsung, SK Hynix, and Micron capital expenditure announcements for 2027.
- TSMC's CoWoS capacity expansion as advanced packaging remains a bottleneck for HBM.
- U.S. semiconductor manufacturing incentives for memory producers.
The semiconductor industry is no longer just a compute story. It is increasingly a memory story—and memory is becoming the strategic bottleneck of the AI economy.
CXMT's G5 platform entering mass production is a milestone for China's semiconductor self-sufficiency. The company's planned NAND push signals that China intends to compete across the full memory stack. But the more consequential story is the one playing out in pricing data and supply forecasts: the AI-driven memory shortage is intensifying, not easing, and the industry's ability to expand capacity will determine how fast AI infrastructure can be deployed.
SK Hynix's talks with Intel and Solidigm's U.S. NAND consideration reflect a broader recognition that memory supply chains must diversify. But the timelines are long, the obstacles are significant, and the equipment required to produce next-generation memory is sold out for years. The winners of the next phase of the semiconductor race will be those who control memory capacity—and the equipment, packaging, and geographic relationships required to produce it.
The CODEW Stat
UBS raised its 2026 AI capital expenditure forecast to $998 billion, attributing nearly all of the increase to rising DRAM and HBM costs—while DRAM contract prices have risen 90–95%, 58–63%, and 13–18% across the first three quarters of 2026, and HBM spot prices run at 4–5x long-term contract levels. Stay updated, and thanks for visiting The CODEW. This is Erwin —see you in the next Semiconductor Watch stories!
News Sources
- Reuters — China's CXMT says new memory-chip platform enters mass production (September 20, 2026)
- Reuters — China's CXMT eyes flash-memory push amid global shortage (September 18, 2026)
- Reuters — SK Hynix in talks with Intel about deal to make memory chips in US (September 16, 2026)
- Reuters — SK Hynix's Solidigm unit is weighing NAND memory chip factory in US (September 18, 2026)
- Reuters — ASML extends chipmaking dominance as customers embrace High NA (September 14, 2026)
- Global Times — CXMT's G5 DRAM platform enters mass production (September 20, 2026)
- TrendForce — Global DRAM industry revenue jumps 59.5% QoQ in Q2 2026
- KB Securities — AI Infra Summit 2026 analysis
- UBS — 2026 AI capital expenditure forecast revision
Reviewed by Erwin Castro
on
Monday, September 21, 2026
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