Semiconductor Watch: The AI Chip Race Enters Its Next Phase And Beyond GPUs
The AI Chip Race Is Entering Its Next Phase: Beyond GPUs
The GPU Era Is Becoming a Broader Chip Race
For three years, the AI semiconductor narrative has been synonymous with a single company and a single product category: GPUs. That framing is now obsolete. As AI workloads diversify—from training trillion-parameter models to running millions of inference queries daily—the silicon required to support them is proliferating. Custom accelerators, advanced packaging, high-bandwidth memory, networking chips, and next-generation lithography are all becoming critical battlegrounds. The AI chip race is no longer about who builds the fastest GPU. It is about who controls the entire stack.
Desktop discrete GPU shipments reached 12.5 million units in Q2 2026, a four-year high, with Nvidia capturing approximately 90% of the market. But the strategic conversation has shifted. Hyperscalers are designing their own silicon at unprecedented scale, and the GPU era is being absorbed into a much larger competition.
Custom Silicon Changes the Competitive Map
The most consequential shift in AI semiconductors is the rise of hyperscaler-designed accelerators. Google has placed its TPU v5p generation into broad external availability and is shipping the inference-oriented Trillium at scale. Amazon's Trainium 2 and Trainium 3, Microsoft's Maia 200, Meta's MTIA, and OpenAI's custom chip program represent a $604 billion market shift away from merchant GPUs.
The strategic rationale is straightforward: hyperscalers spend tens of billions annually on AI compute, and custom silicon offers better performance-per-dollar for their specific workloads while reducing dependence on a single supplier. Google's Virgo Network can now connect 134,000 TPU 8t chips with up to 47 petabits of bandwidth—a scale that makes custom silicon viable not just for inference but for frontier training.
Why this matters: The custom silicon wave is not a rejection of merchant GPUs. It is an insurance policy. Hyperscalers will continue to buy GPUs for workloads where the incumbent ecosystem is unmatched, but they will increasingly route predictable, high-volume workloads to their own silicon. The merchant GPU market is not shrinking—but its share of total AI compute is being diluted by a new class of buyers who are also becoming designers.
Advanced Packaging Becomes the Bottleneck
The AI accelerator is no longer a single chip. It is a system-in-package that integrates compute dies, high-bandwidth memory stacks, and interposers. And the packaging step has become the primary constraint on AI chip supply. TSMC's CoWoS process faces yield challenges when stitching AI accelerators with HBM on a single chip, with steep costs, thick packages, yield risk, and high scrap rates.
The shortage has become so acute that Nvidia scrapped its flagship quad-die Rubin Ultra design because TSMC's CoWoS-L packaging could not control substrate warpage across a four-die 2x2 matrix with 16 HBM4E stacks. Intel's EMIB technology is emerging as a credible alternative, potentially opening the foundry market to competition on packaging rather than just process node. HBM4 has entered mass production with 48GB per module and speeds more than 50% faster than HBM3E, but capacity ramp remains slow.
Why this matters: The packaging bottleneck is not a temporary constraint. It is a structural feature of AI chip design. As chiplets become standard and HBM stacks grow taller, the complexity of assembling them into a working package will only increase. The companies that master advanced packaging will control the pace at which AI compute scales.
High-NA EUV: The Next Manufacturing Frontier
ASML has secured commitments from TSMC, Samsung, and Intel to adopt its next-generation High-NA EUV lithography systems, which cost approximately $400 million each. These machines can print features about 40% smaller than standard EUV systems, potentially cutting manufacturing steps and increasing productivity. Intel, the first adopter, has already processed more than a million wafers with High-NA tools.
TSMC intends to use High-NA in high-volume manufacturing starting in 2030, while Samsung plans to be the first to apply it to advanced DRAM production by 2028. The strategic significance is twofold: High-NA enables continued transistor scaling beyond the limits of standard EUV, and it deepens the industry's dependence on a single Dutch supplier.
Why this matters: ASML's monopoly on EUV—and now High-NA—makes it the most strategically important company in the semiconductor supply chain. No other company can produce the lithography equipment required for leading-edge chips. That concentration of capability is a geopolitical vulnerability as much as a technological milestone.
The Foundry Concentration Problem
TSMC's dominance in advanced logic manufacturing has reached extraordinary levels. The company holds 72.5% of the pure-play foundry market by revenue, with Q2 2026 revenue of nearly $40.2 billion. Samsung Foundry holds just 5.9% share, and SMIC—China's largest foundry—holds only 5%.
Intel is attempting to break this concentration. Its 18A process has achieved 80% yield on the Panther Lake compute tile, a milestone that led the company to shift 80–90% of its Nova Lake processor production in-house, reducing its reliance on TSMC from a planned 60–70% to just 10–20%. Intel is raising up to $20 billion to fund its foundry ambitions.
Why this matters: TSMC's scale advantage—in capacity, yield learning, and customer relationships—remains formidable. But Intel's 18A progress suggests that the foundry market may become more competitive at the leading edge. For AI chip designers, more foundry options mean more leverage and less supply risk.
AI Demand vs. Semiconductor-Cycle Risk
The AI infrastructure buildout has driven hyperscaler capital expenditure to unprecedented levels. The combined 2026 CapEx of Google, Amazon, Meta, Microsoft, and Oracle is projected to exceed $886.7 billion, with North American hyperscalers accounting for nearly 90%. TSMC has raised its 2026 capital expenditure to $60–64 billion.
| Risk Factor | Current Signal | What It Means |
|---|---|---|
| Memory pricing | DRAM contract prices rising sharply; Q1 2026 projections suggest 60% increase | Cost inflation is reaching the consumer and enterprise hardware markets |
| Foundry utilization | Utilization improving; wafer price increases being discussed | Capacity discipline is holding—but expansion is accelerating |
| AI spending pace | Hyperscaler CapEx exceeds $886.7B; no slowdown in sight | Demand is real, but the rate of growth is unsustainable indefinitely |
The AI demand cycle is real, but it is not infinite. The semiconductor industry has always been cyclical, and several warning signs are emerging. If capacity expansion outpaces actual AI usage growth, price drops and inventory reversals will amplify semiconductor stock volatility. The companies that manage capacity discipline alongside technological leadership will be the ones that survive the inevitable correction.
What to Watch Next
- HBM supply: Customer fulfillment rates remain around 60%—watch for whether HBM4 ramp accelerates or stays constrained.
- Advanced packaging capacity: Intel's EMIB adoption and TSMC's CoWoS-L yield improvements will determine AI chip supply in 2027.
- Custom accelerators: Google TPU v7, Amazon Trainium 3, and Microsoft Maia 200 deployments will test whether hyperscaler silicon scales beyond internal workloads.
- High-NA adoption: Intel's throughput data and TSMC's 2030 timeline will shape the next node transition.
- Foundry utilization: TSMC's 72.5% share and Intel's 18A yield trajectory will determine whether the foundry market becomes more competitive or more concentrated.
- AI accelerator orders: Backlog data from GPU and custom silicon vendors will indicate whether demand is holding or softening.
The AI chip race is no longer a GPU race. It is a full-stack competition spanning custom silicon, advanced packaging, HBM, lithography, and foundry capacity.
The leading GPU vendor remains the most important company in AI compute, but its dominance is being contextualized by a broader set of constraints and competitors. Hyperscalers are designing their own accelerators. Advanced packaging is the new bottleneck. High-NA EUV is the next manufacturing frontier. And foundry concentration remains a strategic vulnerability.
The companies that win the next phase of AI semiconductors will not be the ones with the fastest chip. They will be the ones that control the critical layers of the stack—packaging, memory, lithography, and foundry capacity—that determine how fast AI compute can scale.
Sources
- Reuters — ASML extends chipmaking dominance as customers embrace High NA (Sept 14, 2026)
- Tom's Hardware — Desktop graphics card shipments hit four-year high of 12.5 million
- MarketWatch — AI stocks are rebounding; analyst sees no spending slowdown
- TSMC Q2 2026 earnings data
- Intel 18A yield and Nova Lake production reports
- Jon Peddie Research — GPU shipment data
- HBM4 mass production announcements
The CODEW Stat
TSMC holds 72.5% of the pure-play foundry market. Nvidia controls approximately 90% of desktop discrete GPU shipments. Hyperscaler 2026 CapEx exceeds $886.7 billion. And High-NA EUV systems cost $400 million each — with only one company able to build them.
Reviewed by Erwin Castro
on
Wednesday, September 16, 2026
Rating:
